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SDA 525x
Semiconductor Group
50
1998-04-08
Memory Extension (ROMless version only)
The processor is prepared to extend its external program memory space up to
512 Kbytes (
Figure 15
and
16
). For easy handling of existing software and assemblers
this space is split into 8 banks of 64 Kbytes each. The extension concept, based on the
standard 64 K addressing ability, is provided for high effective and easy memory access
with minimum software overhead. There is also no need caring about bank organization
during subroutine processing or interrupts. This is done through address bits A16 – 18,
which are controlled by a special internal circuitry, performing a “delayed banking”. The
operations to the extended memory spaces are controlled by two additional special
function registers called MEX1 and MEX2 (
Figure 17
). The address bits A17 and A18
are implemented at port 4. Programs, using only 128-Kbytes program memory space,
may switch the address function off by setting bits NB, IB and bits MB to ‘1’ followed by
a LJMP. Then port 4 will work properly in port mode. Whenever full address mode is
desired, port 4 bits have to be kept on ‘1’ (
Table 9
). After reset all CB are ‘0’ and P4
latches are set to ‘1’, resulting a ‘0’ at the port 4 pins.
Banking of Program Memory
After reset the bits for current bank (CB) and next bank (NB) are set to zero. This way
the processor starts the same as any 8051 controller at address 00000
H
. Whenever a
jump to another bank is required, the software has to change the bits NB16 – 18 for
initializing the bank exchange (bits CB16 – 18 are read only). After operating the next
LJMP instruction the NB16 – 18 bits (next bank) are copied to CB16 – 18 (current bank)
and will appear at A16 – 18. Only LJMP will do this.
Figure 15
Connecting External Program Memory
UES05663
P4
P3
P2
P1
P0
SDA 5250
A
PSEN
D
A
D
EPROM
OE
Alternative
Connections