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參數(shù)資料
| 型號： | SD1200 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Analog-Interface XGA/SXGA TFT LCD Display Controller |
| 中文描述： | 模擬接口的XGA / SXGA TFT液晶顯示控制器 |
| 文件頁數(shù)： | 26/35頁 |
| 文件大?。?/td> | 245K |
| 代理商： | SD1200 |
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SmartASI C, I nc.
SD1200
PRELIMINARY
DATA SHEET
September, 1998
SmartASIC Confidential
26
and lower bound for 720x400
128H-129H Upper bound of the line number for 720x400 mode,
and lower bound for 640x480
12AH-12BH Upper bound of the line number for 640x480 mode,
and lower bound for 800x600
12CH-12DH Upper bound of the line number for 800x600 mode,
and lower bound for 1024x768
12EH-12FH Upper bound of the line number for 1024x768 mode,
and lower bound for 1280x1024
130H-131H Upper bound of the line number for 1280x1024 mode.
If the input has more line than this threshold, it is
considered INVALID mode
132H[1:0] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
132H[3:2] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
132H[5:4] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
132H[7:6] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
133H[1:0] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
133H[3:2] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
133H[5:4] The polarity of input synchronization signals
Bit 0 is for VSYNC and bit 1 is for HSYNC
134H
The maximum vertical back porch for input video
135H-136H The unit delay used in the external PWM delay
circuitry. If the free-running clock is 1MHz, and the
intended unit delay is 0.2 ns (= 5,000MHz), then a
value of 5,000MHz/1MHz = 5,000 is used here.
137H-139H Maximum time when input VSYNC is off before the
LINK_DWN pin turns ON (unit: clock period of the
free running clock). If the free-running clock is
1MHz, and the intended maximum time is 1 second,
then a value of 1,000,000 us/ 1 us = 1,000,000 is used
here.
13AH-13BH Maximum refresh rate supported by the LCD panel
If the intended maximum refresh rate is 75Hz, and the
free-running clock is 1MHz, then a value of
1000000/75=133,333 is used here
13CH
Maximum source clock rate supported by the SD1200
(unit: frequency of free-running clock)
If the intended maximum clock rate is 60MHz, and
the free-running clock is 1MHz, then a value of 60 is
used here.
If the input signal has a higher frequency than this
value, the VCLK0_X status bit will turn ON.
13DH
Scale factor used when generate look up table for
current even pixel multiplication
13EH
Scale factor used when generate look up table for
current odd pixel multiplication
13FH
Scale factor used when generate look up table for next
even pixel multiplication
Res2 threshold
10
Res3 threshold
10
Res4 threshold
10
Res5 threshold
10
Res6 threshold
10
Mode 640x350
Sync Polarity
Mode 640x400
Sync Polarity
Mode 720x400
Sync Polarity
Mode 640x480
Sync Polarity
Mode 800x600
Sync Polarity
Mode 1024x768
Sync Polarity
Mode 1280x1024
Sync Polarity
Maximum VBP
PWM unit delay
2
2
2
2
2
2
2
8
13
Maximum link off
time
22
Maximum refresh
rate
16
Maximum input
frequency
8
Scale factor CE
8
Scale factor CO
8
Scale factor NE
8
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SD-120049-001 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:Micro-Change Double-Ended Cordset, Straight, Male to Male, 4 Poles, 3.0m (9.84 ) Length, D-Coded Keyway |
| SD-120065-026 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:MICRO-CHANGE COERDSET 3/4/5-POL FEMALE STR SE 22/5 YELLOW PVC CABLE |
| SD-120065-027 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:MICRO-CHANGE CORDSET 3/4/5-POL FEMALE 90 SE 22/3-5 YELLOW PVC CABLE |
| SD-120065-028 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:MICRO-CHANGE CORDSET 3/4/5-POL MA STR SE 22/3-5 YELLOW PVC CABLE |
| SD-120065-030 | 制造商:MOLEX 制造商全稱:Molex Electronics Ltd. 功能描述:MICRO-CHANGE CORDSET 8-POL FEMALE STR SE 24/8 BLACK PUR/PVC CABLE |
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