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參數(shù)資料
| 型號： | S72NS128RD0AHBG40 |
| 廠商： | SPANSION LLC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA133 |
| 封裝： | 8 X 8 MM, 0.50 MM PITCH, LEAD FREE, FBGA-133 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大小： | 619K |
| 代理商： | S72NS128RD0AHBG40 |
May 10, 2010 S72NS-R_00_07
S72NS-R Based MCPs
7
Da ta
Sh e e t
(Adv a n ce
In f o r m ation)
4.
Input/Output Descriptions
Amax – A16
=
Flash Address inputs
ADQ15 – ADQ0
=
Flash multiplexed Address and Data
F-CE#
=
Flash Chip-enable input.
F-OE#
=
Flash Output Enable input. Asynchronous relative to CLK for Burst mode.
F-WE#
=
Flash Write Enable input
F-VCC
=
Flash device power supply (1.7 V to 1.95 V)
F-VCCQ
=
Flash Input/Output Buffer power supply
F-VSS
=
Flash Ground
F-RDY
=
Flash ready output. Indicates the status of the Burst read. VOL = data invalid. VOH = data valid.
F-CLK
=
Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates
burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal
address counter. CLK should remain low during asynchronous access.
F-AVD#
=
Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. VIL = for
asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising
edge of CLK. VIH= device ignores address inputs
F-RST#
=
Flash hardware reset input. VIL= device resets and returns to reading array data
F-ACC
=
Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass
mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions.
D-A12 – D-A0
=
DRAM Address inputs.
D-DQ15 – D-DQ0
=
DRAM Data input/output
D-CLK
=
DRAM System Clock
D-CE#
=
DRAM Chip Select
D-CKE
=
DRAM Clock Enable
D-BA1 – BA0
=
DRAM Bank Select
D-RAS#
=
DRAM Row Address Strobe
D-CAS#
=
DRAM Column Address Strobe
D-UDQM – D-LDQM
=
DRAM Data Input Mask
D-WE#
=
DRAM Write Enable input
D-VSS
=
DRAM Ground
D-VSSQ
=
DRAM Input/Output Buffer ground
D-VCCQ
=
DRAM Input/Output Buffer power supply
D-VCC
=
DRAM device power supply
D-UDQS
=
DRAM Upper Data Strobe, output with read data and input with write data
D-LDQS
=
DRAM Lower Data Strobe, output with read data and input with write data
D-CLK#
=
DDR Clock for negative edge of CLK
RFU
=
Reserved for Future Use
NC
=
No Connect. Can be connected to ground or left floating.
D-TEST
=
Internal Test mode pin for DDR DRAM only. Do not apply any signal on this pin. Can be connected to ground
or left floating.
DNU
=
Do Not Use
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