參數(shù)資料
型號: PIC16F716T-I/SS
廠商: Microchip Technology
文件頁數(shù): 90/136頁
文件大小: 0K
描述: IC PIC MCU FLASH 2KX14 20SSOP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 1,600
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 13
程序存儲器容量: 3.5KB(2K x 14)
程序存儲器類型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
配用: I3-DB16F716-ND - BOARD DAUGHTER ICEPIC3
AC162054-ND - HEADER INTERFACE ICD2 16F716
2007 Microchip Technology Inc.
DS41206B-page 55
PIC16F716
8.3.4
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCP1
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
8.3.5
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency.
8.3.6
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
8.3.7
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
Disable the PWM pin (CCP1) output drivers by
setting the associated TRIS bit.
2.
Set the PWM period by loading the PR2 register.
3.
Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
4.
Set the PWM duty cycle by loading the CCPR1L
register and DC1B bits of the CCP1CON register.
5.
Configure and start Timer2:
Clear the TMR2IF interrupt flag bit of the
PIR1 register.
Set the Timer2 prescale value by loading the
T2CKPS bits of the T2CON register.
Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6.
Enable PWM output after a new PWM cycle has
started:
Wait until Timer2 overflows (TMR2IF bit of
the PIR1 register is set).
Enable the CCP1 pin output driver by
clearing the associated TRIS bit.
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