參數(shù)資料
型號: PDI1394P11BD-S
廠商: NXP SEMICONDUCTORS
元件分類: Buffer和線驅(qū)動
英文描述: TRIPLE LINE TRANSCEIVER, PQFP64
文件頁數(shù): 12/20頁
文件大?。?/td> 148K
代理商: PDI1394P11BD-S
Philips Semiconductors
Product specification
PDI1394P11
3-port physical layer interface
2
1999 Apr 09
853–2150 21222
1.0
FEATURES
3 cable interface ports
Supports 100Mb/s and 200Mb/s transfers
Interfaces to any 1394 standard Link Layer Controller
5V tolerant I/Os with Bus Holders
Single 3.3V supply voltage
Arbitrated (short) Bus Reset (1394a feature)
2.0
DESCRIPTION
The Philips Semiconductors PDI1394P11 is an IEEE1394-1995
compliant Physical Layer interface. The PDI1394P11 provides the
analog physical layer functions needed to implement a three port
node in a cable-based IEEE 1394–1995 network. Additionally, the
device manages bus initialization and arbitration cycles, as well as
transmission and reception of data bits. The Link Layer Controller
interface is compatible with both 3V and 5V Link Controllers. While
providing a maximum transmission data rate of 200 Mb/s, the
PDI1394P11 is compatible with current 100 Mb/s Physical Layer
ICs. The PDI1394P11 is available in the LQFP64 package.
3.0
ORDERING INFORMATION
PACKAGE
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
64-pin plastic LQFP
0
°C to +70°C
PDI1394P11 BD
SOT314-2
4.0
PIN CONFIGURATION
SV00229
TPBIAS3
TPBIAS2
TPBIAS1
TPA1+
TPA1–
TPB1+
TPB1–
AGND
TPA2+
TPA2–
TPB2+
TPB2–
TPA3+
TPA3–
TPB3+
TPB3–
DGND
ISO–
AGND
R1
R0
PLL
VDD
XO
XI
FIL
TER
PLLGND
AGND
RESET–
LPS
PD
DGND
SYSCLK
DGND
CTL0
CTL1
D0
D1
D2
D3
DGND
DVDD
TESTM2
TESTM1
CPS
AGND
C/LKON
PC2
PC1
PC0
CNA
AGND
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PDI1394P11
DVDD
LREQ
DVDD
A
VDD
A
VDD
A
VDD
A
VDD
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