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Chapter 6 XGATE (S12XGATEV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
197
6.3.1.7
XGATE Condition Code Register (XGCCR)
The XGCCR register (
Figure 6-9
) provides access to the RISC core’s condition code register.
Read: In debug mode if unsecured
Write: In debug mode if unsecured
7
0
6
0
5
0
4
0
3
2
1
0
R
W
XGN
XGZ
XGV
XGC
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-9. XGATE Condition Code Register (XGCCR)
Table 6-7. XGCCR Field Descriptions
Field
Description
3
XGN
Sign Flag
— The RISC core’s Sign flag
2
XGZ
Zero Flag
— The RISC core’s Zero flag
1
XGV
Overflow Flag
— The RISC core’s Overflow flag
0
XGC
Carry Flag
— The RISC core’s Carry flag