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參數(shù)資料
| 型號(hào)： | PACDN016M |
| 元件分類： | 參考電壓二極管 |
| 英文描述： | UNIDIRECTIONAL, SILICON, TVS DIODE |
| 封裝： | MINIATURE, MSOP-8 |
| 文件頁(yè)數(shù)： | 3/3頁(yè) |
| 文件大?。?/td> | 290K |
| 代理商： | PACDN016M |
1999 Calirornia Micro Devices Corp. All rights reserved.
11/99
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
CALIFORNIA MICRO DEVICES
PAC DN016
Figure 5
4
8/99
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased
negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a
much higher output impedance to fast transient current spikes. In the VZ equation above, the VSupply term, in reality, is given
by (VDC + Iesd x Rout), where VDC and Rout are the nominal supply DC output voltage and effective output impedance of the
power supply respectively. As an example, a Routof 1 ohm would result in a 10V increment in VZ for a peak Iesd of 10A.
To mitigate these effects, a Zener diode has been integrated into this Protection Array between VP and VN. This Zener diode
clamps the maximum voltage of VP relative to VN at the breakdown voltage of the Zener diode. Although not strictly necessary,
it is recommended that VP be bypassed to the ground plane with a high frequency bypass capacitor. This will lower the
channel clamp voltage, and is especially effective when VP is much lower than the Zener breakdown voltage. The value of this
bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with minimal change in VP.
Typically a value in the 0.1 F to 0.2 F range is adequate for IEC-61000-4-2 level 4 contact discharge protection (8KV). For
higher ESD voltages, the bypass capacitor should be increased accordingly. Ceramic chip capacitors mounted with short
printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor
high frequency characteristics.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic
discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as
possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray series inductance.
Obsolete
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PACDN016S | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:6 CHANNEL ESD PROTECTION ARRAY WITH ZENER SUPPLY CLAMP |
| PACDN017 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:18 CHANNEL ESD PROTECTION ARRAY WITH ZENER SUPPLY CLAMP |
| PACDN017Q | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:18 CHANNEL ESD PROTECTION ARRAY WITH ZENER SUPPLY CLAMP |
| PACDN027 | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:17-CHANNEL TRANSIENT VOLTAGE SUPPRESSOR ARRAY |
| PACDN027Q | 制造商:CALMIRCO 制造商全稱:California Micro Devices Corp 功能描述:17-CHANNEL TRANSIENT VOLTAGE SUPPRESSOR ARRAY |
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