參數(shù)資料
型號: P89LPC9381FDH
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB 3 V byte-erasable flash with 10-bit ADC
封裝: P89LPC9381FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<Always Pb-free,;
文件頁數(shù): 58/59頁
文件大?。?/td> 286K
代理商: P89LPC9381FDH
P89LPC9381_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 8 September 2006
8 of 60
Philips Semiconductors
P89LPC9381
8-bit microcontroller with 10-bit ADC
P1[5]/RST
6
I
P1[5] — Port 1 bit 5 (input only).
I
RST — External Reset input during power-on or if selected via UCFG1. When
functioning as a reset input, a LOW on this pin resets the microcontroller, causing
I/O ports and peripherals to take on their default states, and the processor begins
execution at address 0. Also used during a power-on sequence to force In-System
Programming mode. When using an oscillator frequency above 12 MHz, the
reset input function of P1[5] must be enabled. An external circuit is required
to hold the device in reset at power-up until VDD has reached its specied
level. When system power is removed VDD will fall below the minimum
specied operating voltage. When using an oscillator frequency above
12 MHz, in some applications, an external brownout detect circuit may be
required to hold the device in reset when VDD falls below the minimum
specied operating range.
P1[6]
5
I/O
P1[6] — Port 1 bit 6.
P1[7]/AD04
4
I/O
P1[7] — Port 1 bit 7.
I
AD04 — ADC0 channel 4 analog input.
P2[0] to P2[7]
I/O
Port 2: Port 2 is an 8-bit I/O port with a user-congurable output type. During reset
Port 2 latches are congured in the input only mode with the internal pull-up
disabled. The operation of Port 2 pins as inputs and outputs depends upon the
port conguration selected. Each port pin is congured independently. Refer to
details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
P2[0]/AD07
1
I/O
P2[0] — Port 2 bit 0.
I
AD07 — ADC0 channel 7 analog input.
P2[1]/AD06
2
I/O
P2[1] — Port 2 bit 1.
I
AD06 — ADC0 channel 6 analog input.
P2[2]/MOSI
13
I/O
P2[2] — Port 2 bit 2.
I/O
MOSI — SPI master out slave in. When congured as master, this pin is output;
when congured as slave, this pin is input.
P2[3]/MISO
14
I/O
P2[3] — Port 2 bit 3.
I/O
MISO — When congured as master, this pin is input, when congured as slave,
this pin is output.
P2[4]/SS
15
I/O
P2[4] — Port 2 bit 4.
I
SS — SPI Slave select.
P2[5]/SPICLK
16
I/O
P2[5] — Port 2 bit 5.
I/O
SPICLK — SPI clock. When congured as master, this pin is output; when
congured as slave, this pin is input.
P2[6]
27
I/O
P2[6] — Port 2 bit 6.
P2[7]
28
I/O
P2[7] — Port 2 bit 7.
Table 3.
Pin description …continued
Symbol
Pin
Type
Description
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