參數(shù)資料
            型號(hào): P89LPC9381FDH
            廠商: NXP Semiconductors N.V.
            元件分類: 8位微控制器
            英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB 3 V byte-erasable flash with 10-bit ADC
            封裝: P89LPC9381FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<Always Pb-free,;
            文件頁(yè)數(shù): 41/59頁(yè)
            文件大?。?/td> 286K
            代理商: P89LPC9381FDH
            P89LPC9381_1
            Koninklijke Philips Electronics N.V. 2006. All rights reserved.
            Product data sheet
            Rev. 01 — 8 September 2006
            46 of 60
            Philips Semiconductors
            P89LPC9381
            8-bit microcontroller with 10-bit ADC
            11. Dynamic characteristics
            Table 11.
            Dynamic characteristics (12 MHz)
            VDD = 2.4 V to 3.6 V, unless otherwise specied.
            Tamb = 40 °C to +85 °C for industrial applications, unless otherwise specied.[1][2]
            Symbol
            Parameter
            Conditions
            Variable clock
            fosc =12MHz
            Unit
            Min
            Max
            Min
            Max
            fosc(RC)
            internal RC oscillator frequency
            7.189
            7.557
            7.189
            7.557
            MHz
            fosc(WD)
            internal watchdog oscillator
            frequency
            320
            520
            320
            520
            kHz
            fosc
            oscillator frequency
            0
            12
            -
            MHz
            Tcy(clk)
            clock cycle time
            83
            -
            ns
            fCLKLP
            low-power select clock frequency
            on pin CLKLP
            0
            8
            -
            MHz
            Glitch lter
            tgr
            glitch rejection time
            P1[5]/RST pin
            -
            50
            -
            50
            ns
            any pin except
            P1[5]/RST
            -
            15
            -
            15
            ns
            tsa
            signal acceptance time
            P1[5]/RST pin
            125
            -
            125
            -
            ns
            any pin except
            P1[5]/RST
            50
            -
            50
            -
            ns
            External clock
            tCHCX
            clock HIGH time
            33
            Tcy(clk) tCLCX
            33
            -
            ns
            tCLCX
            clock LOW time
            33
            Tcy(clk) tCHCX
            33
            -
            ns
            tCLCH
            clock rise time
            -8
            -
            8
            ns
            tCHCL
            clock fall time
            -8
            -
            8
            ns
            Shift register (UART mode 0)
            TXLXL
            serial port clock cycle time
            16Tcy(clk)
            -
            1333
            -
            ns
            tQVXH
            output data setup to clock rising
            edge time
            13Tcy(clk)
            -
            1083
            -
            ns
            tXHQX
            output data hold after clock rising
            edge time
            -Tcy(clk) + 20
            -
            103
            ns
            tXHDX
            input data hold after clock rising
            edge time
            -0
            -
            0
            ns
            tXHDV
            input data valid to clock rising edge
            time
            150
            -
            150
            -
            ns
            SPI interface
            fSPI
            SPI operating frequency
            slave
            0
            CCLK
            6
            0
            2.0
            MHz
            master
            -
            CCLK
            4
            -
            3.0
            MHz
            TSPICYC
            SPI cycle time
            19, 20 and 21
            slave
            6
            CCLK
            -
            500
            -
            ns
            master
            4
            CCLK
            -
            333
            -
            ns
            tSPILEAD
            SPI enable lead time
            and 21
            slave
            250
            -
            250
            -
            ns
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