參數(shù)資料
型號: P89LPC9381FDH
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB 3 V byte-erasable flash with 10-bit ADC
封裝: P89LPC9381FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<Always Pb-free,;
文件頁數(shù): 28/59頁
文件大?。?/td> 286K
代理商: P89LPC9381FDH
P89LPC9381_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 8 September 2006
34 of 60
Philips Semiconductors
P89LPC9381
8-bit microcontroller with 10-bit ADC
7.22 Analog comparators
Two analog comparators are provided on the P89LPC9381. Input and output options allow
use of the comparators in a number of different congurations. Comparator operation is
such that the output is a logical one (which may be read in a register and/or routed to a
pin) when the positive input (one of two selectable pins) is greater than the negative input
(selectable from a pin or an internal reference voltage). Otherwise the output is a zero.
Each comparator may be congured to cause an interrupt when the output value changes.
The overall connections to both comparators are shown in Figure 13. The comparators
function to VDD = 2.4 V.
When each comparator is rst enabled, the comparator output and interrupt ag are not
guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt
should not be enabled during that time, and the comparator interrupt ag must be cleared
before the interrupt is enabled in order to prevent an immediate interrupt service.
7.22.1 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single
comparator input pin is used. The value of the internal reference voltage, referred to as
Vref(bg), is 1.23 V ± 10 %.
7.22.2 Comparator interrupt
Each comparator has an interrupt ag contained in its conguration register. This ag is
set whenever the comparator output changes state. The ag may be polled by software or
may be used to generate an interrupt. The two comparators use one common interrupt
vector. If both comparators enable interrupts, after entering the interrupt service routine,
the user needs to read the ags to determine which comparator caused the interrupt.
7.22.3 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down mode.
Fig 13. Comparator input and output connections
comparator 1
CP1
CN1
(P0[4]) CIN1A
(P0[3]) CIN1B
(P0[5]) CMPREF
Vref(bg)
OE1
CO1
CMF1
interrupt
002aac553
CMP1 (P0[6])
EC
CMF2
comparator 2
OE2
CO2
CMP2 (P0[0])
CP2
CN2
(P0[2]) CIN2A
(P0[1]) CIN2B
change detect
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