參數(shù)資料
型號: P89LPC9381FDH
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB 3 V byte-erasable flash with 10-bit ADC
封裝: P89LPC9381FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<Always Pb-free,;
文件頁數(shù): 17/59頁
文件大小: 286K
代理商: P89LPC9381FDH
P89LPC9381_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 8 September 2006
24 of 60
Philips Semiconductors
P89LPC9381
8-bit microcontroller with 10-bit ADC
Brownout detection may be enabled or disabled in software.
If brownout detection is enabled, the brownout condition occurs when VDD falls below the
brownout trip voltage, Vbo (see Table 10 “Static characteristics”), and is negated when VDD
rises above Vbo. If the P89LPC9381 device is to operate with a power supply that can be
below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate
at 2.4 V, otherwise continuous brownout reset may prevent the device from operating.
For correct activation of brownout detect, the VDD rise and fall times must be observed.
Please see Table 10 “Static characteristics” for specications.
7.14.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work
as power comes up initially, before the power supply voltage reaches a level where
brownout detect can work. The POF ag in the RSTSRC register is set to indicate an
initial power-up condition. The POF ag will remain set until cleared by software.
7.15 Power reduction modes
The P89LPC9381 supports three different power reduction modes. These modes are Idle
mode, Power-down mode, and Total Power-down mode.
7.15.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor
when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle
mode.
7.15.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC9381 exits Power-down mode via any reset, or certain interrupts. In Power-down
mode, the power supply voltage may be reduced to the data retention voltage (VDDR). This
retains the RAM contents at the point where Power-down mode was entered. SFR
contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly
recommended to wake up the processor via reset in this case. VDD must be raised to
within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: brownout detect,
watchdog timer, comparators (note that comparators can be powered-down separately),
and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator
has been selected as the system clock and the RTC is enabled.
7.15.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there will be high power consumption. Please use an external low frequency
clock to achieve low power with the RTC running during power-down.
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