參數(shù)資料
型號: P89LPC936FDH
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs
封裝: P89LPC933FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC933HDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html&l
文件頁數(shù): 22/77頁
文件大?。?/td> 537K
代理商: P89LPC936FDH
P89LPC933_934_935_936
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 12 January 2011
29 of 77
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC933/934/935/936 is put into
Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume
operation. Refer to Section 8.15 “Power reduction modes” for details.
(2) P89LPC935/936
Fig 9.
Interrupt sources, interrupt enables, and power-down wake-up sources
002aab081
IE0
EX0
IE1
EX1
BOF
EBO
KBIF
EKBI
interrupt
to CPU
wake-up
(if in power-down)
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF1
ET1
TI & RI/RI
ES/ESR
TI
EST
SI
EI2C
SPIF
ESPI
RTCF
ERTC
(RTCCON.1)
WDOVF
TF0
ET0
any CCU interrupt(1)
ECCU
ENADCI0(2)
ADCI0(2)
ENADCI1
ADCI1
ENBI0(2)
BNDI0(2)
ENBI1
BNDI1
EEIF(2)
EADEE (P89LPC935)
EAD (P89LPC933/934)
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