參數(shù)資料
型號(hào): P89LPC935FHN
廠商: NXP Semiconductors N.V.
元件分類(lèi): 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs
封裝: P89LPC933FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC933HDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html&l
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代理商: P89LPC935FHN
P89LPC933_934_935_936
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 12 January 2011
60 of 77
NXP Semiconductors
P89LPC933/934/935/936
8-bit microcontroller with accelerated two-clock 80C51 core
12. Dynamic characteristics
Table 12.
Dynamic characteristics (12 MHz)
VDD = 2.4 V to 3.6 V unless otherwise specified.
Tamb = 40 °Cto+85 °C for industrial, 40 °Cto+125 °C for extended, unless otherwise specified.[1][2]
Symbol
Parameter
Conditions
Variable clock
fosc =12 MHz Unit
Min
Max
Min
Max
fosc(RC)
internal RC oscillator frequency
7.189
7.557
7.189
7.557
MHz
fosc(WD)
internal watchdog oscillator
frequency
320
520
320
520
kHz
fosc
oscillator frequency
0
12
-
MHz
Tcy(clk)
clock cycle time
83
-
ns
fCLKLP
low-power select clock
frequency
08
-
MHz
Glitch filter
tgr
glitch rejection time
P1.5/RST pin
-
50
-
50
ns
any pin except
P1.5/RST
-
15
-
15
ns
tsa
signal acceptance time
P1.5/RST pin
125
-
125
-
ns
any pin except
P1.5/RST
50
-
50
-
ns
External clock
tCHCX
clock HIGH time
33
Tcy(CLK) tCLCX
33
-
ns
tCLCX
clock LOW time
33
Tcy(CLK) tCHCX
33
-
ns
tCLCH
clock rise time
-8
-
8
ns
tCHCL
clock fall time
-8
-
8
ns
Shift register (UART mode 0)
TXLXL
serial port clock cycle time
16Tcy(CLK)
-
1333
-
ns
tQVXH
output data set-up to clock rising
edge time
13Tcy(CLK)
-
1083
-
ns
tXHQX
output data hold after clock
rising edge time
-Tcy(CLK) +20
-
103
ns
tXHDX
input data hold after clock rising
edge time
-0
-
0
ns
tXHDV
input data valid to clock rising
edge time
150
-
150
-
ns
SPI interface
fSPI
SPI operating frequency
slave
0
CCLK
6
02.0
MHz
master
-
CCLK
4
-3.0
MHz
TSPICYC
SPI cycle time
slave
6
CCLK
-500
-
ns
master
4
CCLK
-333
-
ns
tSPILEAD
SPI enable lead time
slave
250
-
250
-
ns
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