參數(shù)資料
型號: P89LPC9351FDH
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs
中文描述: 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PDSO28
封裝: 4.40 MM, PLASTIC, MO-153, SOT361-1, TSSOP-28
文件頁數(shù): 47/94頁
文件大?。?/td> 629K
代理商: P89LPC9351FDH
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 10 January 2011
51 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.26 Analog comparators
Two analog comparators are provided on the P89LPC9331/9341/9351/9361. Input and
output options allow use of the comparators in a number of different configurations.
Comparator operation is such that the output is a logical one (which may be read in a
register and/or routed to a pin) when the positive input (one of two selectable inputs) is
greater than the negative input (selectable from a pin or an internal reference voltage).
Otherwise the output is a zero. Each comparator may be configured to cause an interrupt
when the output value changes.
In P89LPC9351/9361, the positive inputs of comparators could be amplified by
Programmable Gain Amplifier 1 (PGA1) module. The PGA1 can supply gain factors of 2x,
4x, 8x, or 16x, eliminating the need for external op-amps in the end application.
The overall connections to both comparators are shown in Figure 20 and Figure 21. The
comparators function to VDD =2.4 V.
When each comparator is first enabled, the comparator output and interrupt flag are not
guaranteed to be stable for 10
μs. The corresponding comparator interrupt should not be
enabled during that time, and the comparator interrupt flag must be cleared before the
interrupt is enabled in order to prevent an immediate interrupt service.
When a comparator is disabled the comparator’s output, COn, goes HIGH. If the
comparator output was LOW and then is disabled, the resulting transition of the
comparator output from a LOW to HIGH state will set the comparator flag, CMFn. This will
cause an interrupt if the comparator interrupt is enabled. The user should therefore
disable the comparator interrupt prior to disabling the comparator. Additionally, the user
should clear the comparator flag, CMFn, after disabling the comparator.
Fig 19. SPI single master multiple slaves configuration
002aaa903
master
slave
8-BIT SHIFT
REGISTER
SPI CLOCK
GENERATOR
8-BIT SHIFT
REGISTER
MISO
MOSI
SPICLK
port
MISO
MOSI
SPICLK
SS
slave
8-BIT SHIFT
REGISTER
MISO
MOSI
SPICLK
SS
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