參數(shù)資料
型號: P89LPC9331FDH
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core, 4 kB-8 kB-16 kB 3 V byte-erasable flash with 8-bit ADCs
中文描述: 8-BIT, FLASH, 18 MHz, MICROCONTROLLER, PDSO28
封裝: 4.40 MM, PLASTIC, MO-153, SOT361-1, TSSOP-28
文件頁數(shù): 40/94頁
文件大小: 629K
代理商: P89LPC9331FDH
P89LPC9331_9341_9351_9361
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 10 January 2011
45 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.23.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),
8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored
in RB8 in special function register SCON. The baud rate is variable and is determined by
the Timer 1 overflow rate or the baud rate generator (described in Section 7.23.5 “Baud
7.23.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data
bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.
Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is
received, the 9th data bit goes into RB8 in special function register SCON, while the stop
bit is not saved. The baud rate is programmable to either 1
16 or
1
32 of the CPU clock
frequency, as determined by the SMOD1 bit in PCON.
7.23.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is
the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable
and is determined by the Timer 1 overflow rate or the baud rate generator (described in
7.23.5 Baud rate generator and selection
The P89LPC9331/9341/9351/9361 enhanced UART has an independent baud rate
generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1
and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a
similar manner as Timer 1 but is much more accurate. If the baud rate generator is used,
Timer 1 can be used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 13). Note
that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The
independent baud rate generators use OSCCLK.
7.23.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)
is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is
logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up
when SMOD0 is logic 0.
Fig 13. Baud rate sources for UART (Modes 1, 3)
baud rate modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
timer 1 overflow
(PCLK-based)
baud rate generator
(CCLK-based)
002aaa897
÷2
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