參數(shù)資料
型號(hào): P89LPC932A1FHN
廠商: NXP Semiconductors N.V.
元件分類: 8位微控制器
英文描述: 8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM
封裝: P89LPC932A1FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC932A1FDH/G<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.
文件頁(yè)數(shù): 22/64頁(yè)
文件大小: 319K
代理商: P89LPC932A1FHN
P89LPC932A1_3
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 — 12 March 2007
29 of 64
NXP Semiconductors
P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
7.19.7 Alternating output mode
In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating
pairs for bridge drive control. In this mode the output of these PWM channels are
alternately gated on every counter cycle.
7.19.8 PLL operation
The PWM module features a PLL that can be used to generate a CCUCLK frequency
between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic
PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or
higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output
signal of 32 times the input frequency. This signal is used to clock the timer. The user will
have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the
SFR register TCR21. The PLL frequency can be expressed as shown in Equation 1.
(1)
Where: N is the value of PLLDV[3:0].
Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK
16.
Fig 11. Alternate output mode
TIMER VALUE
002aaa895
0
TOR2
COMPARE VALUE A (or C)
COMPARE VALUE B (or D)
PWM OUTPUT (OCA or OCC)
PWM OUTPUT (OCB or OCD)
PLL frequency
PCLK
N1
+
()
------------------
=
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