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| 型號： | P89LPC930FDH |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit microcontrollers with two-clock 80C51 core 4 kB-8 kB 3 V Flash with 256-byte data RAM |
| 封裝： | P89LPC930FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html<1<week 47, 2004,;P89LPC931FDH<SOT361-1 (TSSOP28)|<<http://www.nxp.com/packages/SOT361-1.html&l |
| 文件頁數(shù)： | 22/55頁 |
| 文件大?。?/td> | 267K |
| 代理商： | P89LPC930FDH |
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Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
Product data
Rev. 05 — 15 December 2004
29 of 55
9397 750 14472
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.17.7
Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device and force the device into ISP mode.
8.17.8
Double buffering
The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the rst character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = ‘0’), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = ‘0’).
8.17.9
Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
8.17.10
The 9th bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| P89LPC930FDH,129 | 功能描述:8位微控制器 -MCU 80C51 4K FL 256B RAM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| P89LPC930FDH.129 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 4K FLASH SMD 89LC930 制造商:NXP Semiconductors 功能描述:IC, 8BIT MCU 4K FLASH, SMD, 89LC930 制造商:NXP Semiconductors 功能描述:IC, 8BIT MCU 4K FLASH, SMD, 89LC930; Controller Family/Series:(8051) 8052; Core Size:8bit; No. of I/O's:26; Supply Voltage Min:2.4V; Supply Voltage Max:3.6V; Digital IC Case Style:TSSOP; No. of Pins:28; Program Memory Size:4KB; RAM ;RoHS Compliant: No |
| P89LPC930FDH129 | 制造商:NXP Semiconductors 功能描述:IC 8BIT MCU 80C51 18MHZ TSSOP-28 |
| P89LPC931 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM |
| P89LPC9311FDH,129 | 功能描述:8位微控制器 -MCU PREF PART P89LPC931FDH RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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