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參數(shù)資料
| 型號： | ORT8850 |
| 廠商： | Lineage Power |
| 英文描述： | Field-Programmable System Chip(現(xiàn)場可編程系統(tǒng)芯片) |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（現(xiàn)場可編程系統(tǒng)芯片） |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 153K |
| 代理商： | ORT8850 |
4
Lucent Technologies Inc.
Preliminary Product Brief
May 2000
ORCA ORT8850 FPSC
Programmable Features
(continued)
I
Built-in testability:
— Full boundary scan (IEEE 1149.1 and Draft
1149.2 JTAG).
— Programming and readback through boundary
scan port compliant to IEEE Draft 1532:D1.7.
— TS_ALL testability function to 3-state all I/O pins.
— New temperature-sensing diode.
I
Improved built-in clock management with program-
mable phase-locked loops (PPLLs) provide optimum
clock modification and conditioning for phase, fre-
quency, and duty cycle from 20 MHz up to 420 MHz.
System Features
I
PCI local bus compliant for FPGA I/Os.
I
Improved PowerPC
*
860 and PowerPCII high-speed
synchronous microprocessor interface can be used
for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA logic, RAMs, and embedded stan-
dard cell blocks. Glueless interface to synchronous
PowerPCprocessors with user-configurable address
space provided.
I
New embedded
AMBA
specification 2.0 AHB sys-
tem bus (ARM
processor) facilitates communication
among the microprocessor interface, configuration
logic, embedded block RAM, FPGA logic, and
embedded standard cell blocks.
I
New
network PLLs meet ITU-T G.811 specifications
and provide clock conditioning for DS-1/E-1 and
STS-3/STM-1 applications.
I
Flexible general purpose PPLLs offer clock multiply
(up to 8x), divide (down to 1/8x), phase shift, delay
compensation, and duty cycle adjustment combined.
I
Variable size bused readback of configuration data
capability with the built-in microprocessor interface
and system bus.
I
Internal, 3-state, and bidirectional buses with simple
control provided by the SLIC.
I
New clock routing structures for global and local
clocking significantly increases speed and reduces
skew (<200 pS for OR4E4).
I
New local clock routing structures allow creation of
localized clock trees.
I
New double-data rate (DDR) and zero-bus turn-
around (ZBT) memory interfaces support the latest
high-speed memory interfaces.
I
New 2x/4x uplink and downlink I/O capabilities inter-
face high-speed external I/Os to reduced speed
internal logic.
I
ORCAFoundry 2000 development system software.
Supported by industry-standard.
I
CAE tools for design entry, synthesis, simulation, and
timing analysis.
I
Meets universal test and operations PHY interface
for ATM (UTOPIA) Levels 1, 2, and 3. Also meets
proposed specifications for UTOPIA Level 4 for
10 Gbits/s interfaces.
* PowerPCis a registered trademark of International Business
Machines, Inc.
AMBA is a trademark of ARM limited.
ARM is a registered trademark of Advanced RISC Machines Lim-
ited.
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|---|---|
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850H | 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850H-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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