參數(shù)資料
型號(hào): OR4E2
廠商: Lineage Power
英文描述: Field-Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門陣列)
中文描述: 現(xiàn)場(chǎng)可編程門陣列(現(xiàn)場(chǎng)可編程門陣列)
文件頁(yè)數(shù): 17/132頁(yè)
文件大小: 2667K
代理商: OR4E2
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Lucent Technologies Inc.
17
Preliminary Data Sheet
August 2000
ORCA Series 4 FPGAs
Programmable Logic Cells
(continued)
The ripple mode can be used in one of four submodes.
The first of these is
adder-subtractor submode
. In
this submode, each LUT generates three separate out-
puts. One of the three outputs selects whether the
carry-in is to be propagated to the carry-out of the cur-
rent LUT or if the carry-out needs to be generated. If
the carry-out needs to be generated, this is provided by
the second LUT output. The result of this selection is
placed on the carry-out signal, which is connected to
the next LUT carry-in or the COUT/FCOUT signal, if it
is the last LUT (K
7
/K
3
). Both of these outputs can be
any equation created from K
Z
[1] and K
Z
[0], but in this
case, they have been set to the propagate and gener-
ate functions.
The third LUT output creates the result bit for each LUT
output connected to F[7:0]/F[3:0]. If an adder/subtrac-
tor is needed, the control signal to select addition or
subtraction is input on F5A/F5C inputs. These inputs
generate the controller input AS. When AS = 0, this
function performs the adder, A + B. When AS = 1, the
function performs the subtractor, A – B. The result bit is
created in one-half of the LUT from a single bit from
each input bus K
Z
[1:0], along with the ripple input bit.
The second submode is the
counter submode
(see
Figure 10). The present count, which may be initialized
via the PFU DIN inputs to the latches/FFs, is supplied
to input K
Z
[0], and then output F[7:0]/F[3:0] will either
be incremented by one for an up counter or decre-
mented by one for a down counter. If an up/down
counter is needed, the control signal to select the direc-
tion (up or down) is input on F5A and F5C. When
F5[A:C], respectively per nibble, is a logic 1, this indi-
cates a down counter and a logic 0 indicates an up
counter.
5-5756(F)
Figure 10. Counter Submode
F7
K
7
[0]
K7
D
Q
C
C
D
Q
Q7
REGCOUT
COUT
F6
K
6
[0]
K6
D
Q
Q6
F4
K
4
[0]
K4
D
Q
Q4
F3
K
3
[0]
K3
D
Q
Q3
F2
K
2
[0]
K2
D
Q
Q2
F1
K
1
[0]
K1
D
Q
Q1
F5
K
5
[0]
K5
D
Q
Q5
F0
K
0
[0]
K0
D
Q
Q0
CIN/FCIN
FCOUT
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