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參數(shù)資料
| 型號： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 9/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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16
MIO
Bits: 6
RT
1= Defines that certain reserved mode commands with data shall be legal and access the I/ O
bus without dependence on host initialization or the BUSY bit in the BASIC STATUS register.
This feature can be used, for example, to set a watchdog timer or read a hardware status
register via the Mil Bus even though the host's state may be undefined.
The I/ O operations are restricted to the data word's lower byte. The mode commands and their
corresponding I/ O addresses in decimal are as follows:
T/R
MODE CODE
I/O ADR(2,1)
I/O WR_L
I/O RD_L
T
24
00
1
0
T
25
10
1
0
R
27
10
0
1
R
28
00
0
1
CMD0
Bits: 5
RT
0= Specifies that after a legal valid command is received, a pulse shall be outputted on a pin
specified by the PULSE field in the corresponding data table tag word. The pulse is activated
together with 2 I/ O control signals (CMDS= 1 and *I/ O WR = 0).
1= Specifies that after a valid legal command is received, the word count/ mode code field
(together with CMDS= 1 and *I/ O WR = 0) shall be outputted on the 5 least significant bits of
the discrete I/ O bus. (Although the protocol chip outputs the entire command, only 5 bits are
outputted by the NHi- RT due to pin- out restrictions).
SRQRST
Bits: 4
RT
1= Specifies that the service request bit in the STATUS word will be reset upon reception of a
valid "Transmit Vector Word" mode command.
SSF_ TF
Bits: 3
RT
0= Specifies that the Sub- System Flag in the Status Word will be determined by the value
of the SSF_ TF pin.
1= Specifies that the Terminal Flag in the Status Word will be determined by the value of the
SSF_ TF pin.
NTAG
Bits: 2
RT
1= Specifies that all the data tables shall be without tag words. This mode of operation can be
used to store received data from several subaddresses into a contiguous block without
interspersed tag words. This feature can facilitate, for example, software upload.
BINH
Bits: 1
BC/ RT
1= Disables reception on bus B.
AINH
Bits: 0
BC/ RT
1= Disables reception on bus A.
4.2.2
POINTER TABLE ADDRESS
Address: 1
R/ W
RT
This register holds the address of the table of pointers used in the RT mode when accessing data
tables. The address is specified as a word address in the lower 4K of the memory space. After
POR the register is initialized to 1000 (hex), with D1 as the LSB of the word address. D0 is a
DON’T CARE and should be set to 0.
Note: The RT pointer table must always be located in the lower 4K words of memory.
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