參數(shù)資料
型號： NHI-1598ET/883
廠商： NATIONAL HYBRID INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69
封裝： 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69
文件頁數(shù)： 69/89頁
文件大?。?/td> 569K
代理商： NHI-1598ET/883
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70
INTPI_ L
Interrupt Priority Input (active low, input).
This signal is used to daisy chain interrupt requests on the host bus. This
signal must be active for the ET to output an interrupt vector.
INTPO_L_DSC
Interrupt Priority Output, Disconnect Signal (output).
This pin has 2 possible functions, depending on the M1760 bit in the RTC
CONTROL register.
If M1760= 0, then the signal is used to daisy chain interrupt requests on the
host bus. When the ET requests an interrupt, this signal is output high;
otherwise, this signal is equal to INTPI_ L.
If M1760= 1, then the pin is set to "1" when the store is disconnected (see
EXTERNAL TERMINAL ADDRESS BUFFER for details).
9.3.0
DISCRETE I/O BUS INTERFACE SIGNALS
I/ O_ RD_ L
I/ O Read (active low, output).
I/ O_ WR_ L
I/ O Write (active low, output).
I/ O_ ADR (2: 1) I/ O Address (outputs).
These three signals can be used to select 4 byte- wide input devices and 4 byte- wide output
devices which reside on the I/ O Data bus.
I/ O_ DAT (7: 0)
I/ O DATA bus (bi- directional).
This bus is used for messages that are mapped to I/O, discreet pulse message
identifiers and setting the Hardwire RT address.
CMDS
Command Strobe (active high, output; 100ns).
This strobe is used for two special I/ O operations. When the strobe is active
during a write cycle (i. e., CMDS= 1, I/ O WR_ L= 0), valid commands or pulses
appear on the I/ O bus (see the CMDO bit in CONTROL register for details).
When the strobe is active during a read cycle (i. e., CMDS= 1, I/ O RD_ L= 0),
the EXTERNAL TERMINAL ADDRESS buffer is accessed.
PLSCMD_ BUS_ JAM
Pulse Command or Bus Jam (active high, output; 100ns).
RT MODE:
Depends on the value of the CMDO bit in the CONTROL
register. If CMDO= 0, then a pulse is issued whenever a
bus message accesses a data table with PULSE (3: 0)= 14
(decimal) in its tag word. If CMDO= 1, then a pulse is issued
whenever a valid broadcast command is received.
Note: The NTAG bit in the CONTROL register must be 0 to
get a pulse output.
BC MODE:
This pin will go high and the BC will halt if a bus jam occurs.
The CPU must then intervene to allow the BC to continue
processing the frame (See configuration register 2 for
details).
MDCDRST
Mode Command Reset Pulse (active high, 400 nS pulse, output).
Pulsed high whenever the mode command "Reset" is received by the
RT. Terminal must be in the RT mode for this pulse to be outputted.
mode.
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