參數(shù)資料
型號: NHI-1598ET/883
廠商: NATIONAL HYBRID INC
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69
封裝: 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69
文件頁數(shù): 68/89頁
文件大?。?/td> 569K
代理商: NHI-1598ET/883
-
69
Power
9.1.0
GENERAL PURPOSE SIGNALS
MRST_ L
Master Reset (active low, input).
Initializes all registers and state machines. ET reads hardwire terminal
address. Reset pulse width is 300ns min. The reset recovery time is 12us
max after the rising edge of the reset pulse.
CLK_ H
Terminal Clock from 10 Mhz oscillator (input).
9.2.0
HOST INTERFACE SIGNALS
H_ DAT (15: 0)
Host Data bus (bi- directional).
H_ ADR (16/14: 1)
Host Address bus (input).
HCS_ L
Chip Select (active low, input).
Selects the NHi-ET. The falling edge of HCS_ L is used to latch the host
address and indicates the start of a host memory cycle. The rising edge
terminates the current cycle. During a host read- modify- write cycle. This
signal must remain active from the beginning to the end of an access cycle.
NOTE: The host should not hold *HCS active for more than 5
microseconds, otherwise timing errors on the Mil-Std Data bus may
occur.
HWRL_ L
Host Write Lower Byte (active low, input).
HWRH_ L
Host Write Upper Byte (active low, input).
HRD_ L
Host Read (active low, input).
DACK_ L
Host Data Transfer Acknowledge (active low, open drain output, 5K internal
pull up).
Indicates to the host that a data transfer has been completed. When the host
reads data, it takes HCS_L low and the HRD_ L low. The ET will indicate
that stable data is on the bus by outputting a low on DTACK_ L. When the
Host writes data, it takes HCS_ L low and HWRL_ L and/ or HWRH_ L low.
The ET then indicates that it has completed the write cycle by outputting a
low on DTACK_ L.
IRQ_ L
Host Interrupt Request (active low, open drain output, 5K internal
pullup).
The IRQ_L will remain low until the Fifo is empty
INTACK_ L
Host Interrupt Acknowledge (active low, input).
When HRD_ L= 0, INTACK_ L= 0, and HCS_ L= 1, an interrupt vector is
popped from the FIFO, the IVR and AVR registers are updated, and the IVR is
outputted onto both the lower and upper bytes of the host data bus, provided
the INTPI_ L is low and the ET is in the RT mode.
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