參數(shù)資料
型號(hào)： NHI-1598ET/883
廠商： NATIONAL HYBRID INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69
封裝： 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69
文件頁(yè)數(shù)： 67/89頁(yè)
文件大?。?/td> 569K
代理商： NHI-1598ET/883
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6
1.0.0
SCOPE
This document defines the functional and electrical specification for National Hybrid's
series of MIL- STD- Data Bus Enhanced Terminals (NHi- ET).
2.0.0
NHi-ET PROTOCOL COMPLIANCE
MIL- STD- 1553A
MIL- STD- 1553B Notices I and II
MIL- STD- 1760B
MCAIR MDC A3818, A5690, A4905, A5332
EFA/ STANAG- 3838 requirements for Eurofighter Aircraft
3.0.0
INTRODUCTION
The NHi- ET is a low cost complete Multi-Protocol Mil- Std- Data Bus Interface between a dual
redundant bus and a host processor. The device functions as a programmable Bus Controller,
Remote Terminal, and Bus Monitor containing a protocol chip, two +5V monolithic transceivers
and 16K or 64K word SRAM. The unit is available packaged in a 1.1" x 1.1" 69 pin ceramic
PGA, or 1.1" x 1.1" 68 pin ceramic quad flatpack. The only external components required are two
coupling transformers.
The NHi- ET appears to the host computer as 16K or 64K words of 16 bit wide memory controlled
by standard RAM signals. The device can thus be easily interfaced with all popular processors
and buses. The built in interrupt controller supports an internal FIFO which retains header
information for queuing up to 6 pending interrupt requests plus an overflow interrupt.
All modes of operation access data tables via pointers residing in RAM which facilitates multiple
buffering. This allows buffers to change without moving data and promotes efficient use of RAM
space. The data tables have programmable sizes and locations.
The NHi-ET is plug in compatible with the popular NHi-RT family of remote terminal with no
changes to hardware or software required. The NHi-ET defaults to the NHi-RT remote terminal
operation on power up.
3.1.0
FEATURES
The NHi- ET is form, fit, and function compatible to the NHi- RT series of parts. This interchange
ability gives the user a high degree of flexibility when configuring a system around the NHi family
of parts.
3.1.1
GENERAL FEATURES
Mulit-Protocol Interface
Single +5 volt supply.
Operates from 10 Mhz clock.
Contains two monolithic +5V transceivers
Appears to host as a Dual Port Double Buffered 16K or 64K x 16 SRAM
Footprint less than 1.25 square inches
Ensures integrity of all shared data and control structures
Built- in interrupt controller
Internal FIFO is configurable to retain header information for queuing up to 6 pending interrupt
requests plus an overflow interrupt, or as a 7 interrupt revolving FIFO
Provides interrupt priority input and output pins for daisy- chaining interrupt requests
Contains a Timer Unit which provides 32 bit RTC (Real- Time- Clock) with 1, 2, 4, 8, 16, 32 and
64 uS internal, or user provided external clock resolution for data and event time tagging.
Interfaces with an 8 bit discrete I/ O bus
Selectable 768/ 672 us Failsafe Timer with complete Testability
Low power CMOS technology
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