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參數(shù)資料
| 型號(hào)： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 66/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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68
When an interrupt is pushed on the FIFO, the priority level determines the circumstances that
caused it. See the AVR and IVR descriptions for details. The following table describes the type of
message which issued the interrupt in the Simultaneous mode:
PRIORITY LEVEL
MESSAGE TYPE
1,2,3,7
REMOTE TERMINAL
5
MONITOR
4
FIFO OVER FLOW
8.5.0
PC BOARD CONSIDERATIONS AND GUIDE LINES
There are a few guide lines which should be observed when mounting the ET and its coupling
transformer on a PC board. The following considerations will prevent layout problems on the
board:
The width of the two land traces for each Bus from the ET to the transformer must be as wide as
possible( 0.1in min width).
The length of the two land traces for each Bus from the ET to the transformer must be as short as
possible( 0.5in max length).
The two land traces for each Bus from the ET to the transformer must be balanced in length and
width.
There should be no ground plane or power plane under transformer or the land traces connecting
the transformer to the ET.
The center tap of the transformer primary must be connected to ground with a heavy short land
trace.
The center tap of the transformer secondary should be left floating.
All the power and ground pins on the ET must be connected.
A 0.1uf capacitor should be connected from each power pin on the ET to ground.
9.0.0
PIN FUNCTIONAL DESCRIPTION
The NHi-ET I/ O pins are divided into 5 families:
General purpose signals
Host interface signals
I/ O bus interface signals
Mil Bus interface signals
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