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參數(shù)資料
| 型號(hào)： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 58/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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This feature can be used to extend the maximum intermessage gap from 4ms to any length, just
by putting a series of NO- OP messages between two operational messages.
8.1.7
32 BIT TIME TAG( 2 WORDS)
The internal time tag resolution is selectable as 1,2,4,8,16,32 or 64us.
8.1.8
BC INTERRUPTS
The following conditions will cause an interrupt to the CPU if they are not masked by the interrupt
mask register.
PRIORITY
INTERRUPT
COMMENT
0
END OF MESSAGE
ENABLED IN MSG GAP WORD
1
END OF FRAME
ENABLED IN REGS 14 & 17
2
ERROR
ERRORS IN RT RESPONSE
3
RETRY
ERROR CAUSED RETRY
4
FIFO OVERFLOW
FIFO IS FULL
5
STATUS SET
STATUS BIT SET OR STATUS ADDRESS
ERROR
6
NO RESPONSE
RT DID NOT RESPOND
7
FAILSAFE TIMEOUT
FAILSAFE TIMEOUT IN NHi-ET ENCODER
The following header information about the BC message that caused the interrupt is pushed on to
the Fifo:
Priority
Message number in frame
Frame A or B
Bus A or B
8.1.9
BUS CONTROLLER EXAMPLE
Now, lets see how we would put the BC into operation!
The following sequence is one approach:
Define various message tables and load them into ram.
Define various message lists and load them withn the addresses of the previously defined
message tables.
At this point, we have the ram loaded with individual messages tables and a number of message
lists. Each message list contains the addresses of several( up to 1024) message tables.
Load the address of the first message list to be used into register 13, Frame A.
Load the total number of messages in that list into register 14, Frame length A.
Load the address of the second message list to be used into register 16, Frame B.
Load the total number of messages in that list into register 17, Frame length B.
Set the mode to BC in register 9.
Set the default frame to A in register 9.
Set the "Default bus" in register 9.
Set "Go alternate frame" in register 14.
Set "int on EOF" in register 14.
Set "Stop at EOF" in register 17.
Set "int on EOF" in register 17.
Set "Start BC" in register 9.
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