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參數(shù)資料
| 型號： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 54/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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57
*INTACK is ignored.
The IVR and AVR can be read from address 4 after performing the hardware interrupt.
If there are more interrupt headers on the FIFO, indicated by the *IRQ remaining low after the
interrupt acknowledge, the procedure is repeated until the FIFO is empty. An empty FIFO is
indicated by the *IRQ line returning high after an interrupt acknowledge and bit 8 in the AVR will
be a "1".
7.2.0
SOFTWARE INTERRUPT ACKNOWLEDGE
If the host CPU does not support a hardware interrupt acknowledge, a software acknowledge can
be performed by reading address 8. This read pops the interrupt header information off the FIFO
and into the IVR and AVR and places their contents on the CPU data bus. The *IRQ line will go
high if the FIFO is empty and remain low if there are additional interrupt headers on the FIFO.
If there are more interrupt headers on the FIFO, indicated by the *IRQ remaining low after the
interrupt acknowledge, the procedure is repeated until the FIFO is empty. An empty FIFO is
indicated by the *IRQ line returning high after an interrupt acknowledge and the MSB in the AVR
will be a "1".
8.0.0
TIPS - HINTS 'N TRICKS
This section will help the USER apply the ET to a system and implement its various features.
8.1.0
BUS CONTROLLER APPLICATIONS
The NHi-ET Bus Controller is flexible, powerful, and very easy to use. The number of operations
required to initialize the device and to examine results of a data message transfer has been
minimized.
The BC function of the NHi-ET employs registers embedded in the protocol chip and its internal
ram to perform its various tasks. These tasks include:
Initiating Message Transfers
Diagnose RT Responses
Take Appropriate Action on Error Conditions
Data Storage
Message lists, containing the addresses of specific messages, are used to develop specific
operational scenarios. The number of message lists and message tables is limited only by the
size of the ram. A list can have up to 1024 messages. A message list is activated by placing its
address in one of the two FRAME START REGISTERS and the list length in one of the FRAME
LENGTH REGISTERS.
8.1.1
BC REGISTERS
This a brief description of the BC registers and their role. Specific bit functions are given in the
address map section of this manual. Only the functions pertinent to the BC are described here.
The following registers are used in the BC function:
8.1.1.1
CONFIGURATION REG 2
Address: 4
Complete EOM and continue.
Goto next message.
Goto EOF and continue.
Stop at end of current message.
Stop at end of current frame.
Abort - Go off line.
Go default frame.
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