參數(shù)資料
型號(hào)： NHI-1598ET/883
廠商： NATIONAL HYBRID INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69
封裝： 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69
文件頁(yè)數(shù)： 31/89頁(yè)
文件大小： 569K
代理商： NHI-1598ET/883
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36
TRANSMIT DATA TABLE
When the host wants to write data to a TRANSMIT data table, the apparent method would be to
load the table with data then exchange corresponding pointers. There is a subtle problem with
this approach. If the host had, within a short period of time prior to this exchange previously
loaded and exchanged these same pointers while the ET had been transmitting data from that
data table , the LOCK bit could still be set in the table the the host was loading during the second
sequence. This is possible because it can take up to 640us to transmit a message, the LOCK bit
being set for the entire time. This could cause new data to be mixed with old data and
transmitted. Avoiding this potential problem is quite simple.
When the host wants to access a TRANSMIT data table, it first reads the LOCK bit in the TAG
WORD of the table belonging to the host. If the LOCK bit is 0, the host proceeds with its access
and loads the data table . If, however, the LOCK bit is 1, this informs the host that the ET is still
accessing that data table. The host should then delay its access until the LOCK bit has been set
to 0 by the ET. When the host finishes updating its TRANSMIT data table, it should set the UPD
bit in the data table's TAG WORD to 1 and then exchange corresponding pointers. This will
ensure that updated data for transmission is made available to the ET as soon as possible and
inform the ET that it will be transmitting fresh data.
Since the host can change its table of pointers at any time, the above mapping scheme can be
used to achieve any desired depth of buffering by simply employing a "round- robin" of pointers.
4.3.4.3
READ- MODIFY- WRITE
The host Read- Modify- Write cycle is used to support CPUs similar to the Motorola 680X0 where
certain instructions (eg:, test and set) require two contiguous accesses to memory. Such
accesses are unique in that the address remains active for both cycles.
4.4.0
BUS CONTROLLER MESSAGE LISTS AND DATA TABLES
The BC is organized and controlled by message lists. Each message list contains the addresses
of data tables associated with the list. A message list can contain up to a maximum of 1023 16
bit addresses. The number of message lists and data tables is limited only by the size of the ram.
The message list mapping scheme is illustrated in the following diagram..
FRAME A/ B
POINTER and FRAME A/ B LENGTH registers have been discussed in a previous section. See
details.
The CPU loads each message list with number of message table pointers determined by a given
scenario requirement. The list is activated by placing its address in the FRAME A or FRAME B
POINTER register and the number of pointers in the list in the corresponding FRAME LENGTH
register.
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