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參數(shù)資料
| 型號(hào)： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 3/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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10
3.3.0
PROTOCOL CHIP DESCRIPTION
The protocol chip contains the following modules:
Host Bus Interface Unit
(HBIU)
I/ O Bus Interface Unit
(IBIU)
Interrupt Controller Unit
(ICU)
Dual Redundant multi protocol Front End
(DRFE)
Message Processor Unit
(MPU)
3.3.1
HOST BUS INTERFACE UNIT
The HBIU provides a standard RAM interface to the host bus. The module performs the following
functions:
Provides NHi- ET device select and decodes host address to select registers.
Transfers data between the NHi-ET and the host (word and byte mode as well as read-
modify- write are supported).
Provides priority input and output for daisy chaining host interrupts.
Outputs *DTACK signal indicating end of bus cycle.
3.3.2
I/O BUS INTERFACE UNIT
The IBIU controls the RAM and I/ O residing on the I/ O bus so that it appears to the host as a
pseudo dual port RAM (i. e., shared memory). The unit implements the following functions:
Arbitrates between host and protocol chip initiated accesses to the RAM and host data
bus.
Decodes address lines to select device (e. g. RAM, external byte- wide I/ O, external
terminal address buffer, command output register).
Generates control signals to access the selected device.
3.3.3
INTERRUPT CONTROL UNIT
The ICU is an 8 input vectored interrupt controller. It contains eight registers as well as a FIFO for
storing pending interrupt vectors.
3.3.3.1
ICU REGISTERS
The ICU contains the following registers
INTERRUPT REQUEST register
(IRR)
INTERRUPT MASK register
(IMR)
INTERRUPT VECTOR register
(IVR)
AUXILIARY VECTOR register
(AVR)
The INTERRUPT REQUEST register samples 8 inputs originating from internal modules. Since
the host can write to this register, all interrupt sequences can be software driven for program
debugging. The inputs and their priorities (level 7 has highest priority) are described in the
following table.
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