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參數(shù)資料
| 型號： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 25/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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30
4.2.30
CONFIGURATION REGISTER 3
Address: 21
R/ W
BC/ MT
This register is used to set global parameters for the BC and the MT.
15
14
13
12
11
10
9
8
RSVD
WORD MT
NTTGDAT
WORD MT
NTAG
WORD MT
NTTAG
MSG MT
NTAG
MSG MT
NTTAG
GLOBAL
RETRY1
GLOBAL
RETRY0
7
6
5
4
3
2
1
0
STAT SET
RETRY
ADR LAT
INHIBIT
BCST MSK
BCST XOR
BUSJAM4
BUSJAM
3
BUSJAM
2
BUSJAM
1
BUSJAM
0
WORD MT NTTGDAT
Bits: 14
MT
0 = A 32 bit time tag is stored with data words and command/ status words.
1 = No time tag on data words. Only command/Status words are time tagged.
WORD MT NTAG
Bits: 13
MT
0 = A Tag word is stored with Data and Command/Status words.
1 = No tag word.
WORD MT NTTAG
Bits: 12
MT
0 = Word Monitor time tag is enabled. Bit 14 determines the time tag format.
1 = No time tagging. Word Monitor time tag is disabled.
MSG MT NTAG
Bits: 11
MT
0 = Tag word is stored with Command/Status words.
1 = No tag word.
MSG_ MT NTTAG
Bits: 10
MT
0 = Message Monitor time tag is enabled. Command/Status words are time tagged.
1 = Message Monitor time tag is disabled.
GLOBAL RETRY
Bits: 9, 8
BC
These bits define a global default retry scenario. If the BC control word defines no retry as the
option for a message, then the global retry is enabled. If the global retry is defined as no retry,
then their will not be a retry for the message.
GLOBAL RETRY OPTIONS
9
8
NO RETRY
0
RETRY ACTIVE BUS
0
1
RETRY ALTERNATE BUS
1
0
RETRY ALTERNATE BUS, THEN ACTIVE BUS
1
STAT SET RETRY
Bits: 7
BC
This bit determines if a retry will be executed when a status word invokes a status set condition.
0 = No retry on status set.
1 = Retry if a status bit is set.
ADR LAT INHIBIT
Bits: 6
RT
This bit determines whether or not the CPU address will be automatically latched by the HCS_ L.
0 = CPU address is automatically latched within 200ns after the falling edge of HCS_ L.
1 = CPU address is manually stored in a transparent when ADR_ LAT_ L input signal is a “1”.
Note:: This option is not available on all parts.
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