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參數(shù)資料
| 型號： | NHI-1598ET/883 |
| 廠商： | NATIONAL HYBRID INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69 |
| 封裝： | 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69 |
| 文件頁數(shù)： | 19/89頁 |
| 文件大?。?/td> | 569K |
| 代理商： | NHI-1598ET/883 |
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25
4.2.21
EXTERNAL TERMINAL ADDRESS REGISTER
Address: 30
R
RT
This register contains information about the hardwire terminal address.
7
6
5
4
3
2
1
0
INVALP
DISCON
TADRP
TADR4
TADR3
TADR2
TADR1
TADR0
The terminal address may be hardwired using I/ O DAT( 5: 0). External pull- down resistors of
4.7K are used to set a low, 64K internal pull- ups set a high. I/ O DAT5 is wired for odd parity in
the address. The hardwire terminal address and its parity can be obtained by reading I/ O
address 30. This address is unique since a read operation activates both the I/ O bus command
strobe and the I/ O bus read signal (i. e., CMDS= 1 and *I/ O RD= 0). As a result, a buffer
containing the terminal address can be selected without decoding address lines.
If an external buffer is not desired, pull- up/ down resistors on the I/ O data bus can be used
instead (see BASIC STATUS register for details). The protocol chip also calculates the terminal
address's parity and compares it to the value obtained from the I/ O bus.
INVALP
Bits: 7
1= Specifies that the terminal address which was read automatically by the protocol chip
following reset (from I/ O address 30) had invalid parity.
DISCON
Bits: 6
0= Specifies that the store is disconnected because a terminal address of 31 was detected on
the I/ O bus for at least 800 nanoseconds.
1= Specifies that the store is connected.
This bit indicates the "disconnected store" condition defined by MIL- STD- 1760A, provided that
the store contains the pull- down resistors used for defining the terminal address (see BASIC
STATUS register for details). After the store is disconnected, the standby state of all I/ O lines
will be high and will therefore define an illegal terminal address of 31.
TADRP
Bits: 5
TADRP equals the value of the terminal address parity read from I/ O address 30.
TADR
Bits: (4:0)
TADR equals the value of the terminal address read from I/ O address 30.
4.2.22
COMMAND OUTPUT PINS
Address: 30
W
RT
Writing a word to the COMMAND OUTPUT PINS (address 30 in the I/ O space) can be used to
simulate the option which outputs 5 bits onto the I/ O bus following valid command reception (see
CMDO bit in the CONTROL register for details). This address is unique since a write operation
activates both the I/ O bus, COMMAND STROBE and the I/ O bus write signal (i. e., CMDS= 1
and *I/ O WR= 0). As a result, the bits can be latched without decoding address lines.
4.2.23
I/ O TAG WORD REGISTER
Address: 31
R/ W
RT
When a data table is mapped to address 32 in the I/ O space, its tag word is contained in this
register. This tag word can be used, for example, to specify an output pulse whenever the data
table is accessed. All other I/ O space data tables are without internal tag words and have no
pulses associated with them.
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