參數(shù)資料
型號(hào)： NHI-1598ET/883
廠商： NATIONAL HYBRID INC
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69
封裝： 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69
文件頁(yè)數(shù)： 15/89頁(yè)
文件大小： 569K
代理商： NHI-1598ET/883
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21
The RTC can be read and reset by the host at any time. Since the RTC consists of 32 bits, at
least 2 memory cycles are required to read all of its value. As a result, a carry- out from the lower
word can occur between the read cycles. A mechanism is therefore provided to solve this
potential difficulty.
If the host reads the RTC as two 16 bit words, *LOCK should be initialized to 1 in the RTC
CONTROL register. In this case, when the host reads the upper word, all 32 bits are latched into
the host output register. The value in the output register remains unchanged until the host
finishes reading the lower word of the RTC.
If the host reads the RTC in bytes, *LOCK should be initialized to 0. In this case, when the host
reads any of the bytes of the RTC, all 32 bits are latched into the host output register and its
value remains unchanged until updating is re- enabled by reading the RTC CONTROL register.
The RTC resolution can be programmed equal to 1, 2, 4, 8, 16, 32, or 64 microseconds.
4.2.10
RTC CONTROL REGISTER
Address: 7
R/ W
BC/ MT/ RT
The RTC CONTROL register controls the RTC as well as having other functions.
15
14
13
12
11
10
9
8
RTC
RESET
LAST
RES2
SYNUPD
*LOCK
SYNRST
RES1
RES0
7
6
5
4
3
2
1
0
M1760
BUSY
OPT
RESET
BUSY
PRESET
4
PRESET
3
PRESET
2
PRESET
1
PRESET
0
RTC RESET
Bits: 15
BC/ MT/ RT
When a "1" is written to RTC RESET, a reset pulse is issued to the RTC. The contents of the
register are not affected by this operation and RTC RESET is always read by the host as "0".
RESET LAST
Bits: 14
BC/ MT/ RT
When a "1" is written to RESET LAST, all the bits in the LAST STATUS REGISTER except the
ADDRESS field and the BUSY bit are set to a "0".
The contents of the register are not affected
by this operation and RESET LAST is always read by the host as "0".
SYNUPD
Bits: 12
RT
1= Specifies that the lower 16 bits of the RTC will be updated whenever a valid mode command
"Synchronize With Data" is received by the ET.
*LOCK
Bits: 11
BC/ MT/ RT
0 = Enables updating of the host output register after the RTC CONTROL register is read (this
feature is needed to support byte wide read cycles).
1 = Enables updating of the host output register after the lower RTC word is read.
SYNRST
Bits: 10
RT
1= Specifies that the RTC shall be reset whenever a valid mode command "Synchronize Without
Data" is received by the ET.
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