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參數(shù)資料
| 型號(hào)： | MX224 |
| 英文描述： | Variable Split Band Inverter with Parallel Control |
| 中文描述： | 可變分割帶逆變器并聯(lián)控制 |
| 文件頁(yè)數(shù)： | 4/17頁(yè) |
| 文件大?。?/td> | 232K |
| 代理商： | MX224 |
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Variable Split Band Inverter
4
MX214/224
1998 MX-COM, Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054
Doc. # 20480112.002
All trademarks and service marks are held by their respective companies.
2.
Signal List
MX214
Pin No.
J/P
7
MX224
Pin No.
J/P
Signal Name
Description
LH
1
LH
1
1
Xtal/Clock
Input to the clock oscillator inverter. A 1MHz crystal
input or externally derived 1MHz clock is injected
here.
Output of the clock oscillator inverter.
8
2
2
2
Xtal
Serial Data Input
9
3
This pin is used to input an 8-bit word representing
the digital control functions. This word is loaded
using the serial data clock and in input in the
following sequence: MUTE, CLEAR,
A1, A2, A3, A4. The
Load
completion. Reference the timing diagram in Figure
8.
In parallel mode, these five digital inputs define the
split point frequency. Each of the 5 input pins has a
1M internal pull-up resistor. See Table 4 for
programming information.
Tx
/
Rx
, A0,
Latch
/
is operated on the
3 – A4
4 – A3
5 – A2
6 – A1
7 – A0
8
3 – A4
4 – A3
5 – A2
6 – A1
7 – A0
8
Programming
Inputs
Tx
/
Rx
This digital input selects the Receive and Transmit
paths and configures upperband and lowerband
filter bandwidths while setting the CTCSS highpass
filter position on the signal path. See Table 2,
Figure 6, and Figure 7. 1M internal pull-up resistor
(Rx).
This pin must be connected to V
SS
for serial loading.
Internal 1M pull-up resistor.
This digital input puts the device into ‘Clear’ or
‘Scramble’ mode by controlling the application of
carrier frequency to the Upper and Lower band
balanced modulators. In ‘Scramble’ mode, the
balanced modulator carrier frequency values are
selected by the split point address A0-A4. See
Table 4. In ‘Clear’ mode, the carriers are disabled
and the balanced modulators are bypassed
internally, i.e. the lower band signal is not added to
the output signal. 1MHz internal pull-up resistor
(Clear).
This digital function is used to disable the Receive or
the Transmit signal paths for rolling code
synchronization while maintaining bias conditions.
Synchronization data can be transmitted during the
Mute periods, as is done in the MX1204 VSB
Scrambler Module. 1M Internal pull-up resistor
(Enable)
This is the externally applied data clock frequency
used to shift input data along in devices wired in the
Serial-loading mode. One full data clock cycle is
required to shift one data bit completely into the
register. See Timing Diagram Figure 8. 1M
Internal pull-up resistor.
13
8
Serial
/
Parallel
9
9
Clear/Scramble
10
10
Enable/Mute
14
10
Serial Clock
Input
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|---|---|
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