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參數(shù)資料
| 型號： | MV8870-1 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | INTERGRATED DTMF RECEIVER |
| 中文描述： | 集成雙音多頻接收器 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 205K |
| 代理商： | MV8870-1 |
MV8870/MV8870-1
3
APPLICATIONS
A simple application circuit is shown in Fig.7. This has a
symmetric guard time circuit, a single-ended analog input and
a dedicated crystal oscillator.
GUARD TIME ADJUSTMENT
In many situations not requiring seperate selection of tone
duration and interdigit pause, the simple steering circuit shown
in Fig.7 is applicable. Component values are chosen according
to the formulae (see Figs. 4, 8a and 8b):-
t
REC
= t
DP
+ t
GTP
t
lD
= t
DA
+ t
GTA
The value of t
DP
is a device parameter (see Dynamic
Characteristics and Fig.5) and t
REC
is the minimum signal
duration to be recognised by the receiver. Likewise t
DA
is a
device parameter (Fig.5) and t
lD
is the minimum time taken to
recognise an interdigit pause. A value for C2 of 0.1
μ
-F is
recommended for most applications, leaving R3 to be selected
by the designer.
Different steering arrangements may be used to select
independantly the guard times for tone present (t
GTP
) and tone
absent (t
GTA
). This may be necessary to meet system
specifications which place both accept and reject limits on both
tone duration and interdigit pause. Guard Time adjustment
also allows the designer to tailor system parameters such as
talk-off and noise immunity. Increasing t
REC
improves talk-off
performance since it reduces the probability that tones
simulated by speech will maintain signal conditions long
enough to be registered. Alternatively a relatively short t
REC
wim a long t
lD
would be appropriate for extremely noisy
environments where fast acquisition time and immunity to tone
drop-outs are required. Design information for guard time
adjustment is shown in Figs. 8a and 8b.
A
B
C
E
F
G
TONE N
TONE N + 1
TONE N + 1
t
DA
t
DA
t
DA
t
DA
t
DP
t
DP
t
DP
t
DP
t
DP
t
DA
V
TSt
t < t
GTP
t < t
GTP
t = t
GTP
t = t
GTA
t = t
GTA
t = t
GTP
t < t
GTA
t
PStD
t
PStD
t
PStD
t
PStD
TONE N
TONE N + 1
DECODED TONE N-1
t
PQ
t
PQ
TONE N
TONE N + 1
D
D
D
V
IN
ESt
St/GT
StD
CODE
CONVERTER
LATCH
OUTPUTS
TOE
Q1 - Q4
EXPLANATION OF EVENTS
A, Tone bursts detected, but tone duration invalid and output latch unchanged.
B. Tone N detected, tone duration valid, output latch updated and new data signalled by
StD.
C. End of tone N detected, tone absent duration valid, but output latch updated until next
valid tone.
D. Outputs switched to high impedance.
E. Tone N + 1 detected, tone duration valid, tone decoded, output latch updated
(although outputs are currently high impedance) and new data signalled by StD.
F. Acceptable dropout of tone N + 1, tone absent duration invalid, StD and output latch
unchanged.
G. End of tone N + 1 detected, tone absent duration valid, StD goes low but output latch
not updated until next valid tone.
NOTES
1. t
time for valid tone present is
a device parameter (see Electrical
Characteristics).
2. t
DA
time for valid tone absent is
a device parameter (see Electrical
Characteristics).
3. t
GTP
and t
GTA
are adjustable via
external RC network at pins 16
and 17 (see Fig. 4).
4. t
PSID
and t
PQ
are propogation
delays given in Electrical
Characteristics.
Figure 5: Timing diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MV8870-1/DP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DTMF Receiver |
| MV8870-1DP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| MV8870-1MP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DTMF Receiver |
| MV8870DG | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DTMF Receiver |
| MV8870HP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DTMF Receiver |
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