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參數(shù)資料
| 型號： | MT90823AL1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | 3V Large Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP100 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, LEAD FREE, MO-112CC, MQFP-100 |
| 文件頁數(shù)： | 5/46頁 |
| 文件大?。?/td> | 643K |
| 代理商： | MT90823AL1 |
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MT90823
Data Sheet
5
Zarlink Semiconductor Inc.
Pin Description
Pin #
Name
Description
84
PLCC
100
MQFP
100
LQFP
120
BGA
1, 11,
30, 54
64, 75
31, 41,
56, 66,
76, 99
28,
38,
53,
63,
73,
96
A1,A2,A12,A13,
B1,B2,B7,B12,
B13,C3,C5,C7,
C9,C11,E3,E11
G3,G11,J3,J11,
L3,L5,L7,L9,L11,
M1,M2,M12,M13
V
SS
Ground.
2, 32,
63
5, 40,
67
37,
64,98
C4,C6,C8,C10,
D3,D11,F3,F11,
H3,H11,K3,K11,
L4,L6,L8,L10
V
DD
+3.3 Volt Power Supply.
3 - 10
68-75
65 -
72
B6,A6,A5,B5,A4,
B4,A3,B3
STo8 - 15
ST-BUS Output 8 to 15 (5 V Tolerant Three-state
Outputs):
Serial data Output stream. These streams
may have data rates of 2.048, 4.096 or 8.192 Mb/s,
depending upon the value programmed at bits DR0 - 1
in the IMS register.
12 -
27
81-96
78 -
93
C1,C2,D1,D2,E1,
E2,F1,F2,G1,G2,
H1,H2,J1,J2,K1,
K2
STi0 - 15
ST-BUS Input 0 to 15 (5 V Tolerant Inputs):
Serial
data input stream. These streams may have data rates
of 2.048, 4.096 or 8.192 Mb/s, depending upon the
value programmed at bits DR0 - 1 in the IMS register.
28
97
94
L1
F0i
Frame Pulse (5 V Tolerant Input):
When the WFPS
pin is low, this input accepts and automatically
identifies frame synchronization signals formatted
according to ST-BUS and GCI specifications. When the
WFPS pin is high, this pin accepts a negative frame
pulse which conforms to WFPS formats.
29
98
95
L2
FE/HCLK
Frame Evaluation / HCLK Clock
(5 V Tolerant
Input):
When the WFPS pin is low, this pin is the frame
measurement input. When the WFPS pin is high, the
HCLK (4.096MHz clock) is required for frame
alignment in the wide frame pulse (WFP) mode.
31
100
97
N1
CLK
Clock (5 V Tolerant Input):
Serial clock for shifting
data in/out on the serial streams (STi/o 0 - 15).
Depending upon the value programmed at bits DR0 - 1
in the IMS register, this input accepts a 4.096, 8.192 or
16.384 MHz clock.
33
6
3
N2
TMS
Test Mode Select (3.3 V Input with internal pull-up):
JTAG signal that controls the TAP controller state
transitions.
34
7
4
M3
TDI
Test Serial Data In (3.3 V Tolerant Input with internal
pull-up):
JTAG serial test instructions and data are
shifted in on this pin.
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PDF描述 |
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| MT90823 | 3V Large Digital Switch |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90823AP | 制造商:Microsemi Corporation 功能描述: |
| MT90823AP1 | 制造商:Microsemi Corporation 功能描述:LOW VOL LARGE DIGITAL SWCH |
| MT90826 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Quad Digital Switch |
| MT90826AG | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays |
| MT90826AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 4K X 4K/2K X 2K/1K X 1K 3.3V 160BGA - Trays |
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