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參數(shù)資料
| 型號： | MT90820AL1 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Large Digital Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PQFP100 |
| 封裝： | 14 X 20 MM, 2.80 MM HEIGHT, LEAD FREE, MO-112CC-1, MQFP-100 |
| 文件頁數(shù)： | 13/37頁 |
| 文件大?。?/td> | 573K |
| 代理商： | MT90820AL1 |
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MT90820
Data Sheet
13
Zarlink Semiconductor Inc.
Table 4 - Internal Register and Address Memory Mapping
Table 5 - Output High Impedance Control
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 32
Ch 33
.
Ch 62
Ch 63
(
Note 3)
1
1
1
1
1
1
1
1
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
0
.
1
1
0
1
.
0
1
Ch 64
Ch 65
.
Ch 126
Ch 127
(
Note 4)
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial interface is at 2 Mb/s mode.
3. Channels 0 to 63 are used when serial interface is at 4 Mb/s mode.
4. Channels 0 to 127 are used when serial interface is at 8 Mb/s mode.
OE bit in Connection
Memory
ODE pin
OSB bit in IMS register
ST-BUS Output Driver Status
0
Don’t Care
Don’t Care
Per Channel
High Impedance
1
0
0
High Impedance
1
0
1
Enable
1
1
0
Enable
1
1
1
Enable
Bit
Name
Description
15 - 6
Unused
Must be zero for normal operation.
5
MBP
Memory Block Program.
When 1, the connection memory block programming feature is
ready for the programming of Connection Memory high bits, bit 11 to bit 15. When 0, this
feature is disabled.
4
MS
Memory Select.
When 0, connection memory is selected for read or write operations. When 1,
the data memory is selected for read operations and connection memory is selected for write
operations. (No microprocessor write operation is allowed for the data memory.)
A7
(Note 1)
A6
A5
A4
A3
A2
A1
A0
Location
Read/Write Address:
Reset Value:
00
H
,
0000
H
.
7
6
5
4
3
2
1
0
8
9
10
11
12
13
STA0
STA1
STA2
STA3
14
15
MS
MBP
0
0
0
0
0
0
0
0
0
0
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相關(guān)代理商/技術(shù)參數(shù) |
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