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MT9072
Data Sheet
193
Zarlink Semiconductor Inc.
12
YL
Receive Y-bit Latch.
When the Y status bit (register address Y12) toggles from zero to one,
or from one to zero, this status bit is latched to one. This bit is cleared when either this
register, or the interrupt status register (register address Y34) is read.
11
AUXPL
Auxiliary Pattern Latch.
When the AUXP status bit (register address Y12) toggles from zero
to one, this status bit is latched to one. This bit is cleared when either this register, or the
interrupt status register (register address Y34) is read.
10
RAIL
Remote Alarm Indication Status Latch.
When the RAI (A) status bit (register address Y12
and Y13) toggles from zero to one, or from one to zero, this status bit is latched to one. This
bit is cleared when either this register, or the interrupt status register (register address Y34) is
read.
9
AISL
Alarm Indication Status Signal Latch.
When the AIS status bit (register address Y12)
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
8
AIS16L
Alarm Indication Signal 16 Status Latch.
When the AIS16 status bit (register address Y12)
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
7
LOSSL
Loss of Signal Status Indication Latch.
When the LOSS status bit (register address Y12)
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
6
RCRC0L
Remote CRC-4 and RAI T10 Latch.
When the RCRC0 status bit (register address Y10)
toggles from zero to one, this status bit is latched to one. This bit is cleared when either this
register, or the interrupt status register (register address Y34) is read.
5
RCRC1L
Remote CRC-4 and RAI T450 Latch.
When the RCRC1 status bit (register address Y10)
toggles from zero to one, this status bit is latched to one. This bit is cleared when either this
register, or the interrupt status register (register address Y34) is read.
4
CEFSL
Consecutively Errored Frame Alignment Signal Latch.
When the CEFS status bit (register
address Y10) toggles from zero to one, this status bit is latched to one. This bit is cleared
when either this register, or the interrupt status register (register address Y34) is read.
3
RFAILL
Remote CRC-4 Multiframe Generator/Detector Failure Latch.
When the status bit (register
address Y10) toggles from zero to one, this status bit is latched to one. This bit is cleared
when either this register, or the interrupt status register (register address Y34) is read.
2
CSYNCL
Receive CRC-4 Synchronization Latch.
When the CSYNC status bit (register address Y10)
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
1
MSYNCL
Receive Multiframe Alignment Latch.
When the MSYNC status bit (register address Y10)
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
0
BSYNCL
Receive Basic Frame Alignment Latch.
When the BSYNC status bit (register address Y10)
toggles from zero to one, or from one to zero, this status bit is latched to one. This bit is
cleared when either this register, or the interrupt status register (register address Y34) is read.
Bit
Name
Functional Description
Table 169 - Sync, CRC-4 Remote, Alarms, MAS and Phase Latched Status Register (Address Y24) (E1)