
MT9072
Data Sheet
153
Zarlink Semiconductor Inc.
8
F6SM
(0)
Framer 6 Sync and Overflow Mask.
This is the mask bit for the F6SVS status bit in the Interrupt
Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit
will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
7
F5HM
(0)
Framer 5 HDLC Mask.
This is the mask bit for the F5HVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
6
F5EM
(0)
Framer 5 Elastic Mask.
This is the mask bit for the F5EVS status bit in the Interrupt Vector
Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
5
F5RM
(0)
Framer 5 Rx Line Mask.
This is the mask bit for the F5RVS status bit in the Interrupt Vector
Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
4
F5SM
(0)
Framer 5 Sync and Overflow Mask.
This is the mask bit for the F5SVS status bit in the Interrupt
Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit
will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
3
F4HM
(0)
Framer 4 HDLC Mask.
This is the mask bit for the F5HVS status bit in the Interrupt Vector
Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
2
F4EM
(0)
Framer 4 Elastic Mask.
This is the mask bit for the F4EVS status bit in the Interrupt Vector
Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
1
F4RM
(0)
Framer 4 Rx Line Mask.
This is the mask bit for the F4RVS status bit in the Interrupt Vector
register(address 911). If this mask bit is one, the corresponding Interrupt Vector status bit will
remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
0
F4SM
(0)
Framer 4 Sync and Overflow Mask.
This is the mask bit for the F4SVS status bit in the Interrupt
Vector Register (address 911). If this mask bit is one, the corresponding Interrupt Vector status bit
will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will
function normally.
Bit
Name
Functional Description
Table 122 - Interrupt Vector 2 Mask Register (Address 903) (T1)