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MT9072
Data Sheet
202
Zarlink Semiconductor Inc.
10
BEII
Frame Alignment Signal (FAS) Bit Error Counter Indication Interrupt.
This bit is one
when the corresponding latched status bit (BEIL, register address Y25) is set, and the
corresponding mask bit is unmasked (BEIM, register address Y45). This bit is cleared when
either this register, or the latched status register is read.
9
CEOI
CRC-4 Error Counter Overflow Interrupt.
This bit is one when the corresponding latched
status bit (CEOL, register address Y25) is set, and the corresponding mask bit is unmasked
(CEOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
8
CEII
CRC-4 Error Counter Indication Interrupt.
This bit is one when the corresponding latched
status bit (CEIL, register address Y25) is set, and the corresponding mask bit is unmasked
(CEIM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
7
VEOI
Bipolar Violation (BPV) Error Counter Overflow Interrupt.
This bit is one when the
corresponding latched status bit (VEOL, register address Y25) is set, and the corresponding
mask bit is unmasked (VEOM, register address Y45). This bit is cleared when either this
register, or the latched status register is read.
6
VEII
Bipolar Violation (BPV) Error Counter Indication Interrupt.
This bit is one when the
corresponding latched status bit (VEIL, register address Y25) is set, and the corresponding
mask bit is unmasked (VEIM, register address Y45). This bit is cleared when either this
register, or the latched status register is read.
5
EEOI
E-Bit Error Counter Overflow Interrupt.
This bit is one when the corresponding latched
status bit (EEOL, register address Y25) is set, and the corresponding mask bit is unmasked
(EEOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
4
EEII
E-Bit Error Counter Indication Interrupt.
This bit is one when the corresponding latched
status bit (EEIL, register address Y25) is set, and the corresponding mask bit is unmasked
(EEIM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
3
PCOI
PRBS CRC-4 Counter Overflow Interrupt.
This bit is one when the corresponding latched
status bit (PCOL, register address Y25) is set, and the corresponding mask bit is unmasked
(PCOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
2
#
not used.
1
PEOI
PRBS Error Counter Overflow Interrupt.
This bit is one when the corresponding latched
status bit (PEOL, register address Y25) is set, and the corresponding mask bit is unmasked
(PEOM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
0
PEII
PRBS Error Counter Indication Interrupt.
This bit is one when the corresponding latched
status bit (PEIL, register address Y25) is set, and the corresponding mask bit is unmasked
(PEIM, register address Y45). This bit is cleared when either this register, or the latched
status register is read.
Bit
Name
Functional Description
Table 179 - Counter Indication and Counter Overflow Interrupt Status Register (Address Y35) (E1)