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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 88/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
88
Zarlink Semiconductor Inc.
In addition to the above per-VC monitoring, the MT90520 also features extra cut-VC monitoring in the UDT case.
This extra functionality is provided on a per-port basis (note that for the UDT mode of operation, per-port is the
equivalent of per-VC). In order to enable this monitoring, the user must configure the MIB Timeout Configuration
Register at byte-address 3000h to set the
Reassembly Cell Loss Integration Period
. The value written in this
field is used by each of the per-port timeout circuits in the MT90520 (i.e., it is a device-wide value and is not
programmable on a per-port basis). The value within the field is expressed in terms of milliseconds and has a
default value of 2.5 s. When any of the 8 per-port timeout counters reaches the timeout period without a cell arriving
on the VC for the port, the
CUT_VC_STATUS
bit for the port is set in the port’s corresponding Timeout
Configuration Register.
4.6.2.2 Late Cell Insertion
In UDT mode, the MT90520 provides per-port CDV monitoring. The user must, on a per-port basis, configure the
LATE_CELL_PERIOD
field in the port’s Timeout Configuration Register. The value within the field is expressed in
terms of 125
μ
s increments, and has a default value of 256 ms. If an internal counter reaches the
LATE_CELL_PERIOD, the
LATE_CELL_STATUS
bit for the “l(fā)ate” VC will be set in the Timeout Configuration
Register for the port.
Additionally, as explained in section “UDT Mode of Operation” on page 73, if the UDT RX_SAR has been
configured by the user to insert dummy cells in late-cell cases and the internal counter reaches
LATE_CELL_PERIOD, a dummy cell will be inserted into the port’s UDT Reassembly Circular Buffer.
4.6.2.3 Underrun Detection
The per-port timeout circuitry provides underrun detection in the UDT mode of operation.
In UDT mode, underruns are detected automatically if the TDM read pointer to a UDT Reassembly Circular Buffer
is ever equal to the UDT RX_SAR’s current write pointer for the corresponding port. An underrun is noted because
the TDM module is reading an address within the UDT Reassembly Circular Buffer which has yet to be written by
the UDT RX_SAR. When a UDT underrun is detected, notification is sent to the UDT RX_SAR, so that it can make
adjustments to its next write pointer value, and so that the MIB statistics can be updated accordingly. At the same
time, notification of the underrun is sent to the TDM module, causing the TDM module to output silence data (i.e., all
ones) on DSTo for the port, until the underrun condition is resolved.
4.6.3 Data RX_SAR Module
Whereas the UDT RX_SAR and SDT RX_SAR handle CBR AAL1 cells, the Data RX_SAR handles non-CBR data
cells. These cells may be AAL5 signalling cells, OAM-type data cells, or any other ATM cells which are received on
VCs which meet the VPI/VCI matching restrictions of the UTOPIA interface of the MT90520.
The Data RX_SAR does not process or manipulate the data cells. Rather, it simply accepts cells which have been
sent to it by the UTOPIA’s VPI/VCI filter mechanism. Once cells are accepted by the Data RX_SAR, they are stored
in a multi-cell circular buffer in external memory, where they can be analyzed by a CPU, under software control.
4.6.3.1 Mode of Operation
Unlike the UDT RX_SAR and the SDT RX_SAR, the Data RX_SAR within the MT90520 can be disabled (default =
“off”). Unless enabled by setting the
Data RX_SAR Enable
bit in the Data RX_SAR Control Register at address
2020h, the Data RX_SAR ignores any incoming data cells, even if they are recognized as data cells by the UTOPIA
module.
The entire 54-byte received cell (i.e., 5 bytes of header, 1 “filler” header byte (UDF2 field) required for the 16-bit
UTOPIA bus, and 48 bytes of payload) is copied to a location in external memory which is identified by the Data
RX_SAR Cell Buffer base address and a hardware write pointer. The base address of the buffer is user-
programmable (in the Data RX_SAR Configuration Register at 2024h), as is the number of cells that can be stored
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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