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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 78/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
78
Zarlink Semiconductor Inc.
UDT Mode of Operation
In “normal” operation (i.e., the UDT RX_SAR’s Fast SN Processing state machine is in “sync”), the UDT RX_SAR is
responsible for transferring a UDT cell received at the UTOPIA interface to a single UDT Reassembly Circular
Buffer in internal memory (corresponding to the TDM port for which the data is destined). However, if it is not in
“sync”, the UDT RX_SAR may also be responsible for inserting up to 7 dummy cells (each filled with 47 bytes of
user-defined data) into the port’s UDT Reassembly Circular Buffer.
Regardless of the state of the Fast SN Processing state machine, a comparison is made between the value of the
UDT RX_SAR’s write pointer and the TDM module’s read pointer, prior to the transfer of each cell to the circular
buffer. The result of the comparison determines whether a slip-error needs to be reported in the MIB statistics, and
may also result in an adjustment of the write pointer’s location before a cell is written to the UDT Reassembly
Circular Buffer (see UDT Overflow and Underrun Detection below).
TDM Data Transfer
Normally the UDT RX_SAR simply transfers 47-byte blocks of data from the UTOPIA interface to a port’s UDT
Reassembly Circular Buffer. However, in the case of a cell loss or misinsertion, up to 7 dummy cells may be
inserted into the circular buffer before the received cell is accepted. If the user has set the
UDT_INSERT_LOST
bit
in the UDT Reassembly Control Register at byte-address 2000h, the UDT RX_SAR is configured to insert the
number of dummy cells calculated by the Fast SN Processing state machine in a cell loss case. On the other hand,
if the user has not set the UDT_INSERT_LOST bit, the UDT RX_SAR will insert a maximum of 2 dummy cells (i.e.,
even if the number of lost cells is greater than 2, only 2 dummy cells may be inserted) into the UDT Reassembly
Circular Buffer in a cell-loss event.
UDT Reassembly Circular Buffers
In the UDT mode of operation, each VC has a specified UDT Reassembly Circular Buffer located in internal
memory. Each buffer is 2048 bytes long and is therefore capable of storing over 43 cells worth of data. The user
can adjust the
Maximum Lead
field in the VC’s UDT Reassembly Control Structure to control the CDV tolerance of
the VC. The Maximum Lead field, as explained in Section , “UDT Reassembly Control Structures,” on page 67, is
user-programmable and determines the maximum distance between the TDM module’s read pointer and the UDT
RX_SAR’s write pointer. In general, the operations of the UDT RX_SAR and the TDM module are synchronized so
that the UDT RX_SAR’s write pointer and the TDM module’s read pointer are always an average distance
(equivalent to Maximum Lead / 2) apart. This phenomenon occurs because most of the time, each time that the
UDT RX_SAR writes a complete cell to the circular buffer, the TDM module reads the complete cell (1:1
relationship).
UDT Overflow and Underrun Detection
The UDT RX_SAR is responsible for generating buffer overflow and buffer
underrun error notifications on a per-VC
basis. In addition to determining if errors occur, the UDT RX_SAR also attempts to compensate for these slips by
adjusting its write pointer. The goal of the write pointer adjustment is to prevent the occurrence of subsequent slips.
When the first cell is about to be written to the UDT Reassembly Circular Buffer for a VC, the UDT RX_SAR looks
at the current value of the TDM read pointer and adjusts the value of its write pointer to be equal to
TDM read
pointer + avg_lead
(where avg_lead is equal to Maximum_Lead / 2). Therefore, if no slips occur, the write pointer
should always be an “average” distance away from the TDM read pointer.
For all subsequent cells, an algorithmic slip-checking routine is performed for every cell which is written to the UDT
Reassembly Circular Buffer, whether it is a dummy cell or a received ATM cell. Each time a cell is to be written to
internal memory, the algorithm looks at the relationship between the UDT RX_SAR’s write pointer and the TDM
module’s read pointer. The algorithm then determines whether the next write to occur will be an “okay” condition, an
overflow, or an underrun. Generally speaking, an “okay” condition means that the UDT RX_SAR is trying to write to
a memory location which is within a distance of Maximum Lead from the TDM read pointer. Overflow conditions are
conditions in which there is a risk of the UDT RX_SAR over-writing data which has yet to be read by the TDM
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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