參數(shù)資料
型號： MT90520
廠商： Zarlink Semiconductor Inc.
英文描述： 8-Port Primary Rate Circuit Emulation AAL1 SAR
中文描述： 8端口基本速率電路仿真AAL1特區(qū)
文件頁數(shù)： 75/180頁
文件大?。?/td> 1736K
代理商： MT90520
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MT90520
Data Sheet
75
Zarlink Semiconductor Inc.
Note **:
The per-port timeout circuitry for late-cell insertion is enabled only when the state machine is entering the
sync state. Therefore, late-cell insertion is only possible when the Fast SN Processing SM is in the “sync” state.
Here are some examples of incoming cell streams containing errors and the corresponding corrective actions taken
by the UDT RX_SAR.
single_cell_loss_
misinsertion
invalid sequence number
- discard cell
start
received cell is in sequence with last received
cell (i.e., single cell loss)
- accept received cell
- declare
lost_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell is in sequence with last in-
sequence cell (i.e., cell misinsertion)
- discard cell (dummy cell already
inserted to take place of
misinserted cell)
- declare
misinserted_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell has a valid sequence number
that is two greater than the last in-sequence
cell (i.e., sequence number protection failure)
- discard received cell (extra
dummy cell was inserted when all
cells were actually received in
order)
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell has valid sequence number, but
doesn’t meet any of the 3 previous criteria
- discard cell
out_of_sync
late_cell_insertion
invalid sequence number
- discard cell
start
received cell has a sequence number one
greater than the originally expected sequence
number (i.e., this appears to be a single-cell
loss)
- accept received cell (dummy cell
was already inserted to replace the
lost cell)
- declare
lost_cell_error
- declare
aal1_seq_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell is that which was originally
expected (i.e., late cell arrival)
- discard cell (because a dummy
cell was already inserted to replace
this one)
- declare
late_cell_error
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
received cell has valid sequence number, but
doesn’t meet either of the 2 previous criteria
Table 15 - Operation of UDT Fast Sequence Number Processing State Machine
- discard cell
- declare
aal1_seq_error
out_of_sync
Description of Error
Sample Incoming Cell
Stream
Cells Used for
Reassembly
Errors Declared
Sequence number protection
failure (looks like single cell
loss)
1 - 3* - 3 - 4 - 5
1 - D
2
- 3* - 4 - 5
1 AAL1 Sequence Error
NOTE:
D indicates the insertion of a dummy cell containing user-programmable data.
Table 16 - Examples of Operation of the UDT Fast Sequence Number Processing State Machine
Current State
Transition Event
Action Taken
Next State
Note
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PDF描述
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相關代理商/技術參數(shù)
參數(shù)描述
MT90520AG 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays
MT90520AG2 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays
MT90528 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR
MT90528AG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR
MT90528AG2 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR
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