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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 73/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
73
Zarlink Semiconductor Inc.
4.6.1.4 Sequence Number Checking (Fast SN Processing State Machine)
After being processed by the Correction/Detection state machine,
all
AAL1 header bytes (whether correctable or
not) and their corresponding validity indicators are passed to the Fast SN Processing state machine standardized
within ITU-T I.363.1. This second portion of the Sequence Number Checking sub-module is responsible for
analyzing the received sequence number values and determining whether the cells are being received in the
correct order. The Fast Sequence Number Processing state machine can detect and compensate for lost cells. In
addition, it can compensate for events which it determines to be misinserted cells.
UDT Mode of Operation
Although based on the state machine standardized in ITU-T I.363.1, additional functionality was added to the UDT
RX_SAR’s state machine in the form of two extra states:
The
single_cell_loss_misinsertion
state was added to provide for the insertion of in-order dummy cells in
the event of a single cell loss or misinsertion. As outlined in the table below, any time that an apparent
single-cell loss occurs, a dummy cell is inserted and then the received cell is accepted into the port’s
Reassembly Circular Buffer. If the event is indeed a single-cell loss, the subsequent received cell is
accepted and the state machine returns to the
sync
state. If the apparent single-cell loss turns out to have
been a cell misinsertion event, the state machine returns to
sync
, but the most recently received (i.e., late)
cell is discarded because a dummy cell was previously inserted in place of the misinserted cell. Similarly, if
the apparent single-cell loss turns out to have been a sequence number protection failure, the state machine
returns to
sync
and the most recently received cell is discarded because a dummy cell was previously
inserted (erroneously) when all of the cells were actually being received in order.
The
late_cell_insertion
state was added as a special user-programmable feature to provide CDV
monitoring. If the user enables the late-cell-checking feature (by setting the CHECK_LATE_ARRIVALS bit in
the UDT Reassembly Control Register at 2000h), when a per-port late-cell timeout counter reaches the
value programmed by the user, a late cell timeout is reached and the Fast SN Processing state machine
transitions into the
late_cell_insertion
state, inserting a single dummy cell on the transition. Once in the
late_cell_insertion
state, the subsequent cell arrival will determine the type of event that occurred. If the
originally expected cell arrives, this is a late cell arrival case; the late cell is discarded and the state machine
returns to
sync
. If the cell which arrives has a sequence number greater by one than that which was
originally expected, a single cell loss has occurred; the received cell is accepted and the state machine
returns to
sync
.
The operation of the state machine is summarized in the following table:
Current State
Transition Event
Action Taken
Next State
Note
x (don’t care)
reset asserted
- none
reset_state
reset_state
reset de-asserted
- none
start
start
invalid sequence number
- discard cell
start
valid sequence number
- discard cell
out_of_sync
out_of_sync
invalid sequence number
- discard cell
start
received cell is not in sequence with previous
cell
- discard cell
out_of_sync
received cell is in sequence with previous cell
- accept received cell
- per-port timeout circuitry is
enabled to permit late-cell
insertions
sync
**
Table 15 - Operation of UDT Fast Sequence Number Processing State Machine
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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