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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 72/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
72
Zarlink Semiconductor Inc.
Based on the ITU-T I.363.1 standard, the Correction/Detection state machine is capable of analyzing a byte of data.
It can then correct a single-bit error in the data or detect (but not correct) a two-bit error. A single-bit error is
classified as the occurrence of either: (i) a parity error or (ii) a CRC error AND a parity error. An uncorrectable error
occurs if a CRC error is detected without a corresponding parity error.
A brief description of the functionality is outlined below.
1. The state machine examines the AAL1 byte and checks for CRC and parity errors, based on hard-wired values
contained within the MT90520. The state machine then outputs two pieces of information for use by the Fast SN
Processing state machine: a validity indicator and a sequence number. The validity signal indicates whether or
not the received byte was determined to be valid (i.e., it was either correct upon arrival, or was corrected by the
Correction/Detection state machine). The sequence number is that which was determined by the Correction/
Detection machine to be the intended sequence number.
2. The type of error-processing which is performed depends upon the current state of the standardized state
machine, either Correction or Detection:
Note *
- When an errored SN cannot be corrected, the Correction/Detection state machine outputs the SN of the
input byte, uncorrected.
3. The most significant bit of the resulting sequence number
(i.e., the CSI bit) may be processed further by the
SRTS clock recovery sub-module (see Section ) or, in the SDT case, by the pointer-processing sub-module (see
“Pointer Processing” on page 80). The 3 least significant bits are
transmitted to the Fast Sequence Number Pro-
cessing state machine as the current cell’s sequence number.
4. At the end of cell processing, two pieces of information related to the Correction/Detection state machine are
updated in the Reassembly Control Structure for the VC: the next state of this state machine (either Correction
or Detection) and the AAL1 Header Errors field.
CRC
Error
Parity
Error
Correctable
Resulting SN
Valid
AAL1 Header
Error
Next State
No
No
Yes
Yes
No
Yes
No
Yes
correct - no need
Yes
No
Yes
SN of input byte
SN of input byte
don’t care
*
corrected SN
Yes
Yes
No
Yes
+0
+1
+1
+1
Correction
Detection
Detection
Detection
Table 13 - Operation of Correction/Detection State Machine in Correction State
CRC
Error
Parity
Error
Correctable
Resulting SN
Valid
AAL1 Header
Error
Next State
No
No
Yes
Yes
No
Yes
No
Yes
correct - no need
No
No
No
SN of input byte
don’t care
*
don’t care
*
don’t care
*
Yes
No
No
No
+0
+1
+1
+1
Correction
Detection
Detection
Detection
Table 14 - Operation of Correction/Detection State Machine in Detection State
相關PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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