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參數(shù)資料
| 型號(hào)： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 61/180頁(yè) |
| 文件大小： | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
61
Zarlink Semiconductor Inc.
In general, Figure 22 should be referred to for explicit details regarding the initialization of the fields within the SDT
Segmentation Control Structures. However, one field needs more explanation, which is provided in the following
text:
Read Pointer Field
When operating in SDT mode, each VC has an associated read pointer, which is configured within the VC's
Segmentation Control Structure. This value, as described in the text accompanying Figure 22, is used by the
TX_SAR to determine the location within the Segmentation Circular Buffers from which the next byte of TDM data
will be read. In general, this field should be initialized to “0”, so that the TX_SAR reads the first data byte that was
written into the buffer by the TDM module. However, in the case of a large number of VCs with small N, the read
pointer value can be used to ease the job of the TX_SAR by distributing the cell generation over more than one
frame. When the read pointer is used to scatter the cell generation, the F (First) bit of the Segmentation Control
Structure should be set to ‘0’.
For example, when N=1 VCs are used, it is possible for the MT90520 to handle up to 256 VCs simultaneously. In
this case, each VC only needs to be serviced once every 47 frames (once enough data from the TDM channel has
been received to complete an ATM cell). Ideally, the Segmentation Control Structures should be configured to
distribute cell generation so that the TX_SAR does not sit idle for 46 frames, and then try to create up to 256 cells in
the 47th frame. In order to eliminate this burstiness problem (and the resulting negative impact on the CDV), the
read pointer for each VC can be set to a non-zero value. For example:
VC_0 read pointer = 0
VC_1 read pointer = 1
...
VC_46 read pointer = 46
VC_47 read pointer = 0
...
By setting the read pointers of various VCs to different values, the user ensures that the TX_SAR will not be
required to generate all of the cells simultaneously. For example, in frame 47, rather than having to generate 256
cells, the TX_SAR will only have to generate 6cells (from VCs numbered 0, 47, 94, 141, 188, 235).
Therefore, when configuring the MT90520 to handle many VCs with low N values, it is recommended that the read
pointers be distributed over multiple frames.
4.5.3.2 SDT Segmentation Pointer Tables
After writing control structures into internal memory, software must configure a pointer table in the same block of
internal memory (i.e., between addresses 80000h and 87FFEh) to permit the TX_SAR hardware to locate the
control structures. An SDT Segmentation Pointer Table must be created on a per-port basis for all ports which are
configured to transmit SDT ATM cells. The table conforms to the format shown in Figure 23 and must start on a 32-
word (64-byte) boundary. There can be up to 32 entries in each table, as there can be a maximum of 32 N=1 VCs
associated with any one TDM port. Each entry in the pointer table contains a field which gives the
word
address of
the SDT Segmentation Control Structure associated with a particular VC. Two extra bits in the pointer table entry
indicate whether the corresponding control structure is enabled, as well as whether this is the final control structure
pointer contained in the table.
For VCs transmitting channels from multiple ports, any one of the ports’ SDT Pointer Table can be chosen to
contain the VC entries. If any SDT Pointer Table entry points to a VC having more than 46 channels, the
TDM_DATA_FORMAT field of the corresponding TDM port’s TDM1 register must be programmed as “11”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT90820 | Large Digital Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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