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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 44/180頁 |
| 文件大?。?/td> | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
44
Zarlink Semiconductor Inc.
4.3.2.2 Reassembly Process
In the reassembly direction, the outgoing data on DSTo[p] is driven with its clock reference on the external pin
SToCLK[p] or the backplane clock, C4M/C2M.
In SDT mode, the frame/multiframe pulse signal is either SToMF[p] in independent mode or F0 in backplane mode.
The frame pulses are not used in UDT mode.
In ST-BUS mode, data and CAS are driven out on DSTo and CSTo/LOSo, respectively, on the falling edge of
SToCLK[p] or C4M/C2M. In Generic mode, data and CAS can be driven out on either the rising or falling edge of
the outgoing clock, depending on the configuration selected by the user.
UDT format
In this format, the data is written by the UDT RX_SAR to a UDT Reassembly Circular Buffer (one per port) in
internal memory. The TDM module retrieves this data and writes it to the port’s TDM Output Buffer. The data is then
converted to a serial stream and sent out on DSTo, driven on the selected edge of SToCLK[p]. SToMF[p] is kept low
by the TDM module. The CSTo/LOSo pin drives out the value specified by the user in the TDM_REASS_LOS bit
(programmed in the per-port TDM Control Register 3).
In the case of an underrun, the TDM reassembly process continues to read from the port’s internal circular buffer,
but ignores the actual data read and instead writes “all ones” data to the TDM Output Buffer. The underrun
detection is performed by the UDT RX_SAR. See Section and Section 4.6.2.3 for more details.
SDT format
In SDT mode, data and CAS are written to the SDT Reassembly Circular Buffers in external memory by the SDT
RX_SAR (one buffer per channel). The data is then extracted from the SDT Reassembly Circular Buffers by the
SDT TDM reassembly process and transferred to the per-port TDM Output Buffers.
Data and CAS are read out of the TDM Output Buffer, converted to separate bit streams and driven out on DSTo
and CSTo/LOSo, on the selected edge of the TDM clock (SToCLK[p] if the device is in independent mode, or the
common clock C4M/C2M if the device is in backplane mode). In DS1-1.544 MHz mode, no framing bit is received in
the ATM cells. Therefore, when the time comes to send out a framing bit (aligned with the frame pulse), the DSTo
line is tristated for the duration of that bit.
The user can select either a multiframe or a frame pulse to be sent out on SToMF[p] by setting the
TDM_PULSE_SEL bit (in the per-port TDM Control Register 1). However, if the device is in backplane mode, only
frame pulses can be sent out on the common frame pulse pin, F0. The user can also select the format of the frame/
multiframe pulse by setting the polarity control bit (TDM_PULSE_POL in TDM Control Register 1). The multiframe
or the frame pulse is driven out on the selected edge of the appropriate TDM clock.
SDT Reassembly Circular Buffers
The main function of the SDT Reassembly Circular Buffers is to store reassembled TDM data and CAS for output
onto the TDM bus. These circular buffers, which are located in external memory, are composed of 16-bit wide
entries, each of which is composed of the following fields, as shown in Figure 12:
MF -
multiframe indicator; this bit is used only when a VC is carrying CAS data (if a VC isn’t carrying CAS,
the MF bits are always zero).
Res -
reserved field; this field always contains a zero.
Turn -
this field contains a copy of the two most-significant bits of the SDT RX_SAR write pointer for the VC.
These bits are used by the TDM module for underrun detection.
CAS -
If CAS data is being processed, this field contains the nibble of data which was last received by this
channel (i.e., in the previous multiframe). CAS data is repeated for an entire multiframe (i.e., 24 consecutive
entries in DS1 case, 16 consecutive entries in E1 case).
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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