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參數(shù)資料
| 型號： | MT90520 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| 中文描述： | 8端口基本速率電路仿真AAL1特區(qū) |
| 文件頁數(shù)： | 15/180頁 |
| 文件大小： | 1736K |
| 代理商： | MT90520 |
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MT90520
Data Sheet
15
Zarlink Semiconductor Inc.
Capable of operating in UTOPIA Level 1 mode (8-bit bus running at up to 25 MHz), for connection to older
devices
Supports up to 256 bidirectional VCCs (Structured Nx64 mode)
VPI/VCI Match and Match Enable filter prevents excessive look-up table accesses to external memory
Cell reception based on look-up table allows flexible VCC assignment for CBR VCCs (allows non-
contiguous VCC assignment)
Automatically eliminates null cells (i.e., VPI and VCI = 0)
Look-up table supports up to 65536 VCC entries
2.6 Segmentation and Reassembly Modules
Supports AAL1 Segmentation and Reassembly for Structured and Unstructured CES as specified in af-vtoa-
0078.000
Supports non-multiframe or multiframe circuit emulation, using AAL1 structure formats as described in af-
vtoa-0078.000: Nx64 Basic Service (single frame structure) or DS1 or E1 Nx64 Service with CAS
(multiframe structure)
Supports transmission and reception of up to 128 TDM channels per VCC in accordance with af-vtoa-
0089.001 (ATM Trunking using AAL1 for Narrowband Services)
Supports Unstructured CES and Structured CES simultaneously on different ports
Supports 8 bidirectional VCCs, carrying 1.544 Mbps or 2.048 Mbps, in Unstructured CES mode
Supports up to 256 bidirectional VCCs, carrying from 1 to 128 DS0 (64 kbps) TDM channels, in Structured
CES mode (up to 256 DS0 channels total)
UDT reassembly works with 8 per-port timing engines for fast processing and low delay variation in
Unstructured CES mode (1 VCC per port, for 8 UDT VCCs total)
Low latency in Unstructured CES mode provided by on-chip CDV buffering which does not require any
external memory
Internal CDV buffers of 2048 bytes for each UDT port
Maximum UDT CDV buffering of
±
4.9 ms in DS1 mode and
±
3.7 ms in E1 mode
External CDV buffers of 1024 bytes for each SDT port
Maximum SDT CDV buffering of ±
63.75 ms (dependent on the Reassembly Circular Buffer size and
number of channels per VC)
Non-CBR data cell transmission and reception for software-implemented SAR function (through non-CBR
Data Cell Buffers in external memory)
Gathers statistical information and provides management statistics for network management through
microprocessor interface
Per VCC monitoring compliant with ATMF CES specification Version 2.0 MIB
Low latency in segmentation and reassembly directions
2.7 Clock Management
Individual, per-port, integrated clock-recovery PLL allows for flexible, independent timing on each TDM port
Per-port Stratum 4 digital PLL supports several clock recovery modes:
Synchronous clocking - generates DS1 or E1 clock from network reference (19.44 MHz or 8 kHz)
Adaptive clocking - recovers clock from received-data buffer fill-level
SRTS - recovers clock from received RTS (residual time stamp) nibbles
Line-rate clocking - PLL locks to incoming DS1 or E1 clock and reduces jitter
Free-running clocks - PLL provides free-running high-accuracy clock for start-up or no-signal conditions (accuracy
limited by MCLK accuracy)
Direct control of PLL output frequency - offset from centre frequency can be configured via CPU
Support for optional external PLL such as MT9042 or MT9044: primary & secondary network references and
primary & secondary LOS references output to external PLL; TDM_CLOCK input from external PLL
Bus clock I/O for operation in backplane mode: C4M/C2M and F0.
相關(guān)PDF資料 |
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|---|---|
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AV | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90528AG2 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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