
MT90503
Data Sheet
38
Zarlink Semiconductor Inc.
4.1.2.1 Extended Indirect Accessing
Extended Indirect Accessing solely employs the registers 0000h to 000Ah to access the 8 MB of addressable
memory space.
Synopsis: the user writes the access address to registers 0000h, 0008h and 000Ah. Then the MT90503 will
read/write to that address and fetch/place the data value from/to register 0004h. For all extended indirect accesses
the INMO_A_DAS bit will be held low.
4.1.2.2 Extended Indirect Writes
The following steps must be executed to perform an extended indirect write:
The software will set access_req [8] in register 0000h (Step 4 above) and the hardware will reset it when the data
write has completed. Therefore, the user can poll this bit to determine when the data write has completed.
4.1.2.3 Extended Indirect Reads
The software will set access_req[8] register 0000h and the hardware will reset it when the data is ready to be read
from register 0004h.
4.1.2.4 Extended Direct Accessing
Extended Direct Accessing employs the high and low address registers to perform page addressing. The address
within the page is provided directly by the CPU address bus. Similarly the data is fetched/placed directly on the
CPU data bus.
Synopsis: the user writes the access address to registers 0008h and 000Ah but this performs only the page
addressing. Upon assertion of the address within the page the MT90503 will read/write the data with respect to that
address. The INMO_A_DAS bit is set when the data read/write occurs. When operating the CPU interface in direct
mode with a 16-bit data bus, extended_a[19:16], are employed for the lower address word register 000Ah.
1
Write the upper address, extended_a[32:20], to register 0008h. This write may be not be required if previous
value holds true.
2
Write the lower address, extended_a[19:4], to register 000Ah. This write may be not be required if previous
value holds true.
3
Write the write data, extended_data[15:0], to register 0004h. This write may be not be required if previous
value holds true.
4
Write write_enable, extended_parity, access_req=‘1’ and extended_a [3:1] in a single access to register
0000h.
5
Read the access_req bit located in the Control Register[8] to determine when the write has completed.
1
Write the upper address, extended_a[32:20], to register 0008h. This write may be not be required if previous
value holds true.
2
Write the lower address, extended_a[19:4], to register 000Ah. This write may be not be required if previous
value holds true.
3
Write write_enable = 00, access_req=‘1’ and extended_a [3:1] in a single access to register 0000h.
4
Wait until access_req is cleared, then read the data from the data field extended_data[15:0], register 0004h.
5
Optional parity check may be ascertained by performing a read on the extended_parity[15:14], register
0000h.