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參數(shù)資料
| 型號(hào)： | MT90503 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 2048VC AAL1 SAR |
| 中文描述： | 2048VC AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 70/233頁(yè) |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503 |
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MT90503
Data Sheet
70
Zarlink Semiconductor Inc.
4.3.6.2 Support of Partially-Filled Cells
The MT90503 is capable of supporting partially-filled cells, as long as the number of channels in the VC is smaller
or equal to the cell fill. A single transmit event scheduler can be created to accommodate several sizes of AAL1,
CBR-AAL0 or AAL5-VTOA ATM cells. AAL1 with pointer ATM cells can be used by this format, since the number of
data bytes per ATM cell is always constant. For example, the 240-entry transmit event scheduler is capable of
accommodating partially-filled cells of 4-, 5-, 6-, 8-, 10-, 12-, 15-, 16-, 20-, 24-, 30-, or 40-bytes per cell.
4.3.6.3 TX_SAR FIFO
The TX_SAR transmits cells contained in its data cell FIFO when there are no events to be processed. The TX
SAR’s data FIFO can be used to store AAL0 cells as well as OAM cells, therefore, CPU-based OAM cell generation
is supported.
4.4 RX_SAR Module
The RX_SAR module performs processing on ATM cells received from the UTOPIA module. Cells placed in the
RX_SAR input FIFO by the UTOPIA module are read, processed, and then written into the appropriate multi-cell
circular buffer in external control memory. The processing involves identifying the VC corresponding to the cell,
examining the cell for errors, determining where to place the data, and monitoring the status of circular buffers. The
RX_SAR module also directs data cells to the data cell FIFO from which the CPU can read them.
The RX_SAR module does not connect to any external pins, interfacing instead with the UTOPIA module, CPU
interface, and external memory controller
.
Global pointers are shared between the RX_SAR and TDM modules.
ATM cells that are received by the MT90503 are processed by the UTOPIA module and can be directed to any of
three TX output FIFOs or to the 32-cell RX_SAR input FIFO. Those cells that are forwarded to the RX_SAR are
directed to the SAR portion (cells to be formatted into TDM streams), to the data cell portion (to be examined by the
CPU), or to both.
For cells directed to the SAR portion, the RX_SAR uses control information in the RX_SAR Control Structures
(Section 4.4.2) to extract the payload data from the received cell and store it into TDM channel RX Circular Buffers
located in external data memory.
4.4.1 Treatment of Data Cells
Data cells, such as those containing OAM information, are placed in a programmable length FIFO in external
control memory. The length of the FIFO is stored in register 070Eh. The CPU can read a data cell at any time, after
obtaining the address of the FIFO (register 070Ch) and the read pointer (register 0708h).
The CPU can be alerted to the presence of data cells via an interrupt that triggers if either of two events occur: the
interrupt can be generated when the FIFO becomes more than half full or the interrupt can be generated if a data
cell has been present in the FIFO for longer than a programmable period of time (registers 0720h, 0722h). This
interrupt can be enabled through register 0220h.
When ready to process the information, the CPU obtains a read pointer to the information from register 0708h and
reads the information through 26 word accesses.
Cells with the OAM bit set in the PTI portion of the header can be directed to the data cell FIFO on a per VC basis.
The same is true for non-OAM cells. In addition, unknown non-OAM cells, and/or unknown OAM cells can also be
sent to the data cell FIFO (all unknown non-OAM cells are directed to the same location(s)).
4.4.2 Control Structure
For each VC directed to the SAR portion of the RX_SAR, an RX_SAR control structure exists in external control
memory. The structure, similar to that of the TX_SAR, contains information on how to process a cell including:
what type of traffic is being carried (AAL1, CBR-AAL0, AAL5-VTOA)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90503AG | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| MT90520 | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90503AG | 制造商:Microsemi Corporation 功能描述: |
| MT90520 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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