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參數(shù)資料
| 型號(hào)： | MT90503 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 2048VC AAL1 SAR |
| 中文描述： | 2048VC AAL1特區(qū) |
| 文件頁(yè)數(shù)： | 16/233頁(yè) |
| 文件大?。?/td> | 1341K |
| 代理商： | MT90503 |
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MT90503
Data Sheet
16
Zarlink Semiconductor Inc.
1.0 Introduction
1.1 Functional Overview of the MT90503
The MT90503 is an AAL1 SAR, which offers a highly integrated solution for interfacing telecom bus-based systems
with ATM networks. The device has the capability of simultaneously processing 2048 bi-directional channels of 64
Kbps. The MT90503 can be connected directly to an H.100 or H.110 compatible bus. The device also offers the
capability of using Channel Associated Signalling (CAS) to support Circuit Emulation Service (CES) for Structured
Data Transfer (SDT).
The interface to the TDM port is provided by a TDM bus, which consists of 32 bi-directional serial TDM data
streams at 2.048, 4.096, or 8.192 Mbps, therefore allowing for 2048 bi-directional TDM channels operating at 64
kbps. This TDM bus is compatible with the ECTF H.100 and H.110 specifications.
The interface to the ATM domain is provided by three UTOPIA ports (Ports A, B, and C). All three of the UTOPIA
ports can operate in ATM (master) or PHY (slave) mode.
Port A is a UTOPIA Level 2 interface which can operate at up to 50 MHz using a 16- or an 8-bit data bus. This port
is capable of operating in ATM-mode (single-PHY), in PHY-mode (slave-mode or level 1), or in slave MPHY-mode
(Level 2).
Port B is a UTOPIA Level 2 interface, which can operate at up to 50 MHz using a 16- or an 8-bit data bus but does
not support bus addressing. This port is capable of operating in ATM-mode (single-PHY), in PHY-mode
(slave-mode).
Port C is a UTOPIA Level 1 interface which can operate at up to 50 MHz using an 8-bit data bus. This port is
capable of operating in ATM-mode (master-mode), or in PHY-mode (slave-mode). The MT90503 is capable of
performing a UTOPIA loopback from any incoming UTOPIA port to any outgoing UTOPIA port, including a loopback
to the port of origin. The loopback capability could be used for dual fibre ring applications.
Figure 3 shows the data flow from the H.100/H.110 bus to the TX UTOPIA interface.
Figure 3 - Transmit Data Flow - TDM to UTOPIA
H.100/H.110 Bus
TDM Bus
TX SAR Internal
Memory
TX UTOPIA
Interface
UTOPIA Output
UTOPIA Cell
Router
UTOPIA Input FIFO
Circular Buffers[15:8]
(External Data Memory)
Path Controlled by TDM Module
Path Controlled by TX SAR Module
Path Controlled by UTOPIA Module
Time-Slot Memories
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90503AG | CLIP, STRAIN RELIEF, 50WAY; For use with:820 Series Tripolarized Wiremount Sockets; Ways, No. of:50; Material:Metal; Connector type:Strain Relief RoHS Compliant: Yes |
| MT90520 | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT9072 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MT9072AB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90503AG | 制造商:Microsemi Corporation 功能描述: |
| MT90520 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8-Port Primary Rate Circuit Emulation AAL1 SAR |
| MT90520AG | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90520AG2 | 制造商:Microsemi Corporation 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays 制造商:Zarlink Semiconductor Inc 功能描述:ATM SAR 2.048MBPS 2.5V CBR 456BGA - Trays |
| MT90528 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:28-Port Primary Rate Circuit Emulation AAL1 SAR |
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