參數(shù)資料
型號(hào): MT9046AN
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: T1/E1 System Synchronizer with Holdover
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO48
封裝: 0.300 INCH, MO-118AA, SSOP-48
文件頁(yè)數(shù): 16/34頁(yè)
文件大?。?/td> 508K
代理商: MT9046AN
MT9046
Data Sheet
16
Zarlink Semiconductor Inc.
Phase Lock Time
This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal
and output signal are not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many factors which include:
initial input to output phase difference
initial input to output frequency difference
synchronizer loop filter
synchronizer limiter
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. And better (smaller) phase slope performance (limiter) results in longer lock times. The MT9046 loop filter and
limiter were optimized to meet the AT&T TR62411 jitter transfer and phase slope requirements. Consequently,
phase lock time, which is not a standards requirement, may be longer than in other applications. See AC Electrical
Characteristics - Performance for Maximum Phase Lock TIme.
MT9046 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference
within approximately 500 ms.
Description
State
Input Controls
Freerun
Normal
(PRI)
Normal
(SEC)
Holdover
(PRI)
Holdover
(SEC)
MS2
MS1
RSEL
PCCi
S0
S1
S2
S1H
S2H
0
0
0
0
S1
-
S1 MTIE
S1
S1 MTIE
0
0
0
1
S1
-
S1 MTIE
S1 MTIE
S1 MTIE
0
0
1
X
S2
S2 MTIE
-
S2 MTIE
S2 MTIE
0
1
0
X
/
S1H
/
-
/
0
1
1
X
/
S2H
S2H
/
-
1
0
X
X
-
S0
S0
S0
S0
Legend:
- No Change
/ Not Valid
MTIE State change occurs with TIE Corrector Circuit
Refer to Control State Diagram for state changes to and from Auto-Holdover State
Table 4 - Control State Table
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